4dd5e9c60e
Movdir64b is special for its mem operand, 67 prefex can not only modify its add size, so it's mem base and index reg should be the same type as source reg, such as movdir64b (%rdx), rcx, and could not be movdir64b (%edx), rcx. Now llvm-mc can encode the asm 'movdir64b (%edx), rcx' but the result is the same as 'movdir64b (%edx), ecx', which offend users' intention, while gcc will object this action and give a warning. I add 3 new mem descriptions to let llvm-mc to report the same error. Reviewed By: skan, craig.topper Differential Revision: https://reviews.llvm.org/D145893
777 lines
24 KiB
C++
777 lines
24 KiB
C++
//===- X86Operand.h - Parsed X86 machine instruction ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
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#define LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
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#include "MCTargetDesc/X86IntelInstPrinter.h"
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#include "MCTargetDesc/X86MCTargetDesc.h"
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#include "X86AsmParserCommon.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/SMLoc.h"
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#include <cassert>
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#include <memory>
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namespace llvm {
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/// X86Operand - Instances of this class represent a parsed X86 machine
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/// instruction.
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struct X86Operand final : public MCParsedAsmOperand {
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enum KindTy { Token, Register, Immediate, Memory, Prefix, DXRegister } Kind;
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SMLoc StartLoc, EndLoc;
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SMLoc OffsetOfLoc;
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StringRef SymName;
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void *OpDecl;
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bool AddressOf;
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/// This used for inline asm which may specify base reg and index reg for
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/// MemOp. e.g. ARR[eax + ecx*4], so no extra reg can be used for MemOp.
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bool UseUpRegs = false;
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struct TokOp {
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const char *Data;
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unsigned Length;
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};
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struct RegOp {
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unsigned RegNo;
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};
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struct PrefOp {
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unsigned Prefixes;
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};
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struct ImmOp {
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const MCExpr *Val;
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bool LocalRef;
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};
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struct MemOp {
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unsigned SegReg;
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const MCExpr *Disp;
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unsigned BaseReg;
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unsigned DefaultBaseReg;
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unsigned IndexReg;
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unsigned Scale;
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unsigned Size;
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unsigned ModeSize;
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/// If the memory operand is unsized and there are multiple instruction
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/// matches, prefer the one with this size.
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unsigned FrontendSize;
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/// If false, then this operand must be a memory operand for an indirect
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/// branch instruction. Otherwise, this operand may belong to either a
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/// direct or indirect branch instruction.
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bool MaybeDirectBranchDest;
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};
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union {
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struct TokOp Tok;
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struct RegOp Reg;
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struct ImmOp Imm;
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struct MemOp Mem;
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struct PrefOp Pref;
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};
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X86Operand(KindTy K, SMLoc Start, SMLoc End)
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: Kind(K), StartLoc(Start), EndLoc(End), OpDecl(nullptr),
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AddressOf(false) {}
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StringRef getSymName() override { return SymName; }
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void *getOpDecl() override { return OpDecl; }
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/// getStartLoc - Get the location of the first token of this operand.
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SMLoc getStartLoc() const override { return StartLoc; }
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/// getEndLoc - Get the location of the last token of this operand.
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SMLoc getEndLoc() const override { return EndLoc; }
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/// getLocRange - Get the range between the first and last token of this
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/// operand.
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SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); }
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/// getOffsetOfLoc - Get the location of the offset operator.
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SMLoc getOffsetOfLoc() const override { return OffsetOfLoc; }
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void print(raw_ostream &OS) const override {
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auto PrintImmValue = [&](const MCExpr *Val, const char *VName) {
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if (Val->getKind() == MCExpr::Constant) {
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if (auto Imm = cast<MCConstantExpr>(Val)->getValue())
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OS << VName << Imm;
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} else if (Val->getKind() == MCExpr::SymbolRef) {
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if (auto *SRE = dyn_cast<MCSymbolRefExpr>(Val)) {
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const MCSymbol &Sym = SRE->getSymbol();
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if (const char *SymNameStr = Sym.getName().data())
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OS << VName << SymNameStr;
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}
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}
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};
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switch (Kind) {
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case Token:
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OS << Tok.Data;
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break;
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case Register:
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OS << "Reg:" << X86IntelInstPrinter::getRegisterName(Reg.RegNo);
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break;
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case DXRegister:
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OS << "DXReg";
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break;
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case Immediate:
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PrintImmValue(Imm.Val, "Imm:");
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break;
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case Prefix:
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OS << "Prefix:" << Pref.Prefixes;
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break;
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case Memory:
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OS << "Memory: ModeSize=" << Mem.ModeSize;
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if (Mem.Size)
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OS << ",Size=" << Mem.Size;
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if (Mem.BaseReg)
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OS << ",BaseReg=" << X86IntelInstPrinter::getRegisterName(Mem.BaseReg);
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if (Mem.IndexReg)
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OS << ",IndexReg="
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<< X86IntelInstPrinter::getRegisterName(Mem.IndexReg);
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if (Mem.Scale)
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OS << ",Scale=" << Mem.Scale;
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if (Mem.Disp)
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PrintImmValue(Mem.Disp, ",Disp=");
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if (Mem.SegReg)
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OS << ",SegReg=" << X86IntelInstPrinter::getRegisterName(Mem.SegReg);
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break;
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}
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}
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StringRef getToken() const {
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assert(Kind == Token && "Invalid access!");
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return StringRef(Tok.Data, Tok.Length);
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}
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void setTokenValue(StringRef Value) {
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assert(Kind == Token && "Invalid access!");
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Tok.Data = Value.data();
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Tok.Length = Value.size();
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}
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unsigned getReg() const override {
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assert(Kind == Register && "Invalid access!");
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return Reg.RegNo;
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}
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unsigned getPrefix() const {
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assert(Kind == Prefix && "Invalid access!");
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return Pref.Prefixes;
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}
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const MCExpr *getImm() const {
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assert(Kind == Immediate && "Invalid access!");
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return Imm.Val;
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}
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const MCExpr *getMemDisp() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Disp;
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}
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unsigned getMemSegReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.SegReg;
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}
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unsigned getMemBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.BaseReg;
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}
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unsigned getMemDefaultBaseReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.DefaultBaseReg;
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}
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unsigned getMemIndexReg() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg;
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}
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unsigned getMemScale() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.Scale;
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}
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unsigned getMemModeSize() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.ModeSize;
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}
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unsigned getMemFrontendSize() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.FrontendSize;
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}
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bool isMaybeDirectBranchDest() const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.MaybeDirectBranchDest;
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}
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bool isToken() const override {return Kind == Token; }
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bool isImm() const override { return Kind == Immediate; }
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bool isImmSExti16i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti16i8Value(CE->getValue());
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}
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bool isImmSExti32i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti32i8Value(CE->getValue());
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}
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bool isImmSExti64i8() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti64i8Value(CE->getValue());
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}
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bool isImmSExti64i32() const {
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if (!isImm())
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return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE)
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return true;
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// Otherwise, check the value is in a range that makes sense for this
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// extension.
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return isImmSExti64i32Value(CE->getValue());
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}
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bool isImmUnsignedi4() const {
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if (!isImm()) return false;
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// If this isn't a constant expr, reject it. The immediate byte is shared
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// with a register encoding. We can't have it affected by a relocation.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return false;
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return isImmUnsignedi4Value(CE->getValue());
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}
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bool isImmUnsignedi8() const {
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if (!isImm()) return false;
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// If this isn't a constant expr, just assume it fits and let relaxation
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// handle it.
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getImm());
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if (!CE) return true;
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return isImmUnsignedi8Value(CE->getValue());
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}
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bool isOffsetOfLocal() const override { return isImm() && Imm.LocalRef; }
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bool needAddressOf() const override { return AddressOf; }
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bool isMem() const override { return Kind == Memory; }
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bool isMemUnsized() const {
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return Kind == Memory && Mem.Size == 0;
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}
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bool isMem8() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 8);
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}
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bool isMem16() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 16);
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}
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bool isMem32() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 32);
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}
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bool isMem64() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 64);
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}
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bool isMem80() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 80);
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}
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bool isMem128() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 128);
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}
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bool isMem256() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 256);
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}
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bool isMem512() const {
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return Kind == Memory && (!Mem.Size || Mem.Size == 512);
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}
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bool isSibMem() const {
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return isMem() && Mem.BaseReg != X86::RIP && Mem.BaseReg != X86::EIP;
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}
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bool isMemIndexReg(unsigned LowR, unsigned HighR) const {
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assert(Kind == Memory && "Invalid access!");
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return Mem.IndexReg >= LowR && Mem.IndexReg <= HighR;
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}
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bool isMem64_RC128() const {
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return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem128_RC128() const {
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return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem128_RC256() const {
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return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM15);
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}
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bool isMem256_RC128() const {
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return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM15);
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}
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bool isMem256_RC256() const {
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return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM15);
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}
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bool isMem64_RC128X() const {
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return isMem64() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem128_RC128X() const {
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return isMem128() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem128_RC256X() const {
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return isMem128() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem256_RC128X() const {
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return isMem256() && isMemIndexReg(X86::XMM0, X86::XMM31);
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}
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bool isMem256_RC256X() const {
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return isMem256() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem256_RC512() const {
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return isMem256() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
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}
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bool isMem512_RC256X() const {
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return isMem512() && isMemIndexReg(X86::YMM0, X86::YMM31);
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}
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bool isMem512_RC512() const {
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return isMem512() && isMemIndexReg(X86::ZMM0, X86::ZMM31);
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}
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bool isMem512_GR16() const {
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if (!isMem512())
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return false;
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if (getMemBaseReg() &&
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!X86MCRegisterClasses[X86::GR16RegClassID].contains(getMemBaseReg()))
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return false;
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return true;
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}
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bool isMem512_GR32() const {
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if (!isMem512())
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return false;
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if (getMemBaseReg() &&
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!X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemBaseReg()) &&
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getMemBaseReg() != X86::EIP)
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return false;
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if (getMemIndexReg() &&
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!X86MCRegisterClasses[X86::GR32RegClassID].contains(getMemIndexReg()) &&
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getMemIndexReg() != X86::EIZ)
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return false;
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return true;
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}
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bool isMem512_GR64() const {
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if (!isMem512())
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return false;
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if (getMemBaseReg() &&
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!X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemBaseReg()) &&
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getMemBaseReg() != X86::RIP)
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return false;
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if (getMemIndexReg() &&
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!X86MCRegisterClasses[X86::GR64RegClassID].contains(getMemIndexReg()) &&
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getMemIndexReg() != X86::RIZ)
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return false;
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return true;
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}
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bool isAbsMem() const {
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return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
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!getMemIndexReg() && getMemScale() == 1 && isMaybeDirectBranchDest();
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}
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bool isAVX512RC() const{
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return isImm();
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}
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bool isAbsMem16() const {
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return isAbsMem() && Mem.ModeSize == 16;
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}
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bool isMemUseUpRegs() const override { return UseUpRegs; }
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bool isSrcIdx() const {
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return !getMemIndexReg() && getMemScale() == 1 &&
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(getMemBaseReg() == X86::RSI || getMemBaseReg() == X86::ESI ||
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getMemBaseReg() == X86::SI) && isa<MCConstantExpr>(getMemDisp()) &&
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cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
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}
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bool isSrcIdx8() const {
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return isMem8() && isSrcIdx();
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}
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bool isSrcIdx16() const {
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return isMem16() && isSrcIdx();
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}
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bool isSrcIdx32() const {
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return isMem32() && isSrcIdx();
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}
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bool isSrcIdx64() const {
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return isMem64() && isSrcIdx();
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}
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bool isDstIdx() const {
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return !getMemIndexReg() && getMemScale() == 1 &&
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(getMemSegReg() == 0 || getMemSegReg() == X86::ES) &&
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(getMemBaseReg() == X86::RDI || getMemBaseReg() == X86::EDI ||
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getMemBaseReg() == X86::DI) && isa<MCConstantExpr>(getMemDisp()) &&
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cast<MCConstantExpr>(getMemDisp())->getValue() == 0;
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}
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bool isDstIdx8() const {
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return isMem8() && isDstIdx();
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}
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bool isDstIdx16() const {
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return isMem16() && isDstIdx();
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}
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bool isDstIdx32() const {
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return isMem32() && isDstIdx();
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}
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bool isDstIdx64() const {
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return isMem64() && isDstIdx();
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}
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bool isMemOffs() const {
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return Kind == Memory && !getMemBaseReg() && !getMemIndexReg() &&
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getMemScale() == 1;
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}
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bool isMemOffs16_8() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 8);
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}
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bool isMemOffs16_16() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 16);
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}
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bool isMemOffs16_32() const {
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return isMemOffs() && Mem.ModeSize == 16 && (!Mem.Size || Mem.Size == 32);
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}
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bool isMemOffs32_8() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 8);
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}
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bool isMemOffs32_16() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 16);
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}
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bool isMemOffs32_32() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 32);
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}
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bool isMemOffs32_64() const {
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return isMemOffs() && Mem.ModeSize == 32 && (!Mem.Size || Mem.Size == 64);
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}
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bool isMemOffs64_8() const {
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|
return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 8);
|
|
}
|
|
bool isMemOffs64_16() const {
|
|
return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 16);
|
|
}
|
|
bool isMemOffs64_32() const {
|
|
return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 32);
|
|
}
|
|
bool isMemOffs64_64() const {
|
|
return isMemOffs() && Mem.ModeSize == 64 && (!Mem.Size || Mem.Size == 64);
|
|
}
|
|
|
|
bool isPrefix() const { return Kind == Prefix; }
|
|
bool isReg() const override { return Kind == Register; }
|
|
bool isDXReg() const { return Kind == DXRegister; }
|
|
|
|
bool isGR32orGR64() const {
|
|
return Kind == Register &&
|
|
(X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
|
|
}
|
|
|
|
bool isGR16orGR32orGR64() const {
|
|
return Kind == Register &&
|
|
(X86MCRegisterClasses[X86::GR16RegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::GR32RegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::GR64RegClassID].contains(getReg()));
|
|
}
|
|
|
|
bool isVectorReg() const {
|
|
return Kind == Register &&
|
|
(X86MCRegisterClasses[X86::VR64RegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::VR128XRegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::VR256XRegClassID].contains(getReg()) ||
|
|
X86MCRegisterClasses[X86::VR512RegClassID].contains(getReg()));
|
|
}
|
|
|
|
bool isVK1Pair() const {
|
|
return Kind == Register &&
|
|
X86MCRegisterClasses[X86::VK1RegClassID].contains(getReg());
|
|
}
|
|
|
|
bool isVK2Pair() const {
|
|
return Kind == Register &&
|
|
X86MCRegisterClasses[X86::VK2RegClassID].contains(getReg());
|
|
}
|
|
|
|
bool isVK4Pair() const {
|
|
return Kind == Register &&
|
|
X86MCRegisterClasses[X86::VK4RegClassID].contains(getReg());
|
|
}
|
|
|
|
bool isVK8Pair() const {
|
|
return Kind == Register &&
|
|
X86MCRegisterClasses[X86::VK8RegClassID].contains(getReg());
|
|
}
|
|
|
|
bool isVK16Pair() const {
|
|
return Kind == Register &&
|
|
X86MCRegisterClasses[X86::VK16RegClassID].contains(getReg());
|
|
}
|
|
|
|
void addExpr(MCInst &Inst, const MCExpr *Expr) const {
|
|
// Add as immediates when possible.
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
|
|
Inst.addOperand(MCOperand::createImm(CE->getValue()));
|
|
else
|
|
Inst.addOperand(MCOperand::createExpr(Expr));
|
|
}
|
|
|
|
void addRegOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::createReg(getReg()));
|
|
}
|
|
|
|
void addGR32orGR64Operands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
MCRegister RegNo = getReg();
|
|
if (X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
|
|
RegNo = getX86SubSuperRegister(RegNo, 32);
|
|
Inst.addOperand(MCOperand::createReg(RegNo));
|
|
}
|
|
|
|
void addGR16orGR32orGR64Operands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
MCRegister RegNo = getReg();
|
|
if (X86MCRegisterClasses[X86::GR32RegClassID].contains(RegNo) ||
|
|
X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo))
|
|
RegNo = getX86SubSuperRegister(RegNo, 16);
|
|
Inst.addOperand(MCOperand::createReg(RegNo));
|
|
}
|
|
|
|
void addAVX512RCOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
addExpr(Inst, getImm());
|
|
}
|
|
|
|
void addImmOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
addExpr(Inst, getImm());
|
|
}
|
|
|
|
void addMaskPairOperands(MCInst &Inst, unsigned N) const {
|
|
assert(N == 1 && "Invalid number of operands!");
|
|
unsigned Reg = getReg();
|
|
switch (Reg) {
|
|
case X86::K0:
|
|
case X86::K1:
|
|
Reg = X86::K0_K1;
|
|
break;
|
|
case X86::K2:
|
|
case X86::K3:
|
|
Reg = X86::K2_K3;
|
|
break;
|
|
case X86::K4:
|
|
case X86::K5:
|
|
Reg = X86::K4_K5;
|
|
break;
|
|
case X86::K6:
|
|
case X86::K7:
|
|
Reg = X86::K6_K7;
|
|
break;
|
|
}
|
|
Inst.addOperand(MCOperand::createReg(Reg));
|
|
}
|
|
|
|
void addMemOperands(MCInst &Inst, unsigned N) const {
|
|
assert((N == 5) && "Invalid number of operands!");
|
|
if (getMemBaseReg())
|
|
Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
|
|
else
|
|
Inst.addOperand(MCOperand::createReg(getMemDefaultBaseReg()));
|
|
Inst.addOperand(MCOperand::createImm(getMemScale()));
|
|
Inst.addOperand(MCOperand::createReg(getMemIndexReg()));
|
|
addExpr(Inst, getMemDisp());
|
|
Inst.addOperand(MCOperand::createReg(getMemSegReg()));
|
|
}
|
|
|
|
void addAbsMemOperands(MCInst &Inst, unsigned N) const {
|
|
assert((N == 1) && "Invalid number of operands!");
|
|
// Add as immediates when possible.
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
|
|
Inst.addOperand(MCOperand::createImm(CE->getValue()));
|
|
else
|
|
Inst.addOperand(MCOperand::createExpr(getMemDisp()));
|
|
}
|
|
|
|
void addSrcIdxOperands(MCInst &Inst, unsigned N) const {
|
|
assert((N == 2) && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
|
|
Inst.addOperand(MCOperand::createReg(getMemSegReg()));
|
|
}
|
|
|
|
void addDstIdxOperands(MCInst &Inst, unsigned N) const {
|
|
assert((N == 1) && "Invalid number of operands!");
|
|
Inst.addOperand(MCOperand::createReg(getMemBaseReg()));
|
|
}
|
|
|
|
void addMemOffsOperands(MCInst &Inst, unsigned N) const {
|
|
assert((N == 2) && "Invalid number of operands!");
|
|
// Add as immediates when possible.
|
|
if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(getMemDisp()))
|
|
Inst.addOperand(MCOperand::createImm(CE->getValue()));
|
|
else
|
|
Inst.addOperand(MCOperand::createExpr(getMemDisp()));
|
|
Inst.addOperand(MCOperand::createReg(getMemSegReg()));
|
|
}
|
|
|
|
static std::unique_ptr<X86Operand> CreateToken(StringRef Str, SMLoc Loc) {
|
|
SMLoc EndLoc = SMLoc::getFromPointer(Loc.getPointer() + Str.size());
|
|
auto Res = std::make_unique<X86Operand>(Token, Loc, EndLoc);
|
|
Res->Tok.Data = Str.data();
|
|
Res->Tok.Length = Str.size();
|
|
return Res;
|
|
}
|
|
|
|
static std::unique_ptr<X86Operand>
|
|
CreateReg(unsigned RegNo, SMLoc StartLoc, SMLoc EndLoc,
|
|
bool AddressOf = false, SMLoc OffsetOfLoc = SMLoc(),
|
|
StringRef SymName = StringRef(), void *OpDecl = nullptr) {
|
|
auto Res = std::make_unique<X86Operand>(Register, StartLoc, EndLoc);
|
|
Res->Reg.RegNo = RegNo;
|
|
Res->AddressOf = AddressOf;
|
|
Res->OffsetOfLoc = OffsetOfLoc;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
return Res;
|
|
}
|
|
|
|
static std::unique_ptr<X86Operand>
|
|
CreateDXReg(SMLoc StartLoc, SMLoc EndLoc) {
|
|
return std::make_unique<X86Operand>(DXRegister, StartLoc, EndLoc);
|
|
}
|
|
|
|
static std::unique_ptr<X86Operand>
|
|
CreatePrefix(unsigned Prefixes, SMLoc StartLoc, SMLoc EndLoc) {
|
|
auto Res = std::make_unique<X86Operand>(Prefix, StartLoc, EndLoc);
|
|
Res->Pref.Prefixes = Prefixes;
|
|
return Res;
|
|
}
|
|
|
|
static std::unique_ptr<X86Operand> CreateImm(const MCExpr *Val,
|
|
SMLoc StartLoc, SMLoc EndLoc,
|
|
StringRef SymName = StringRef(),
|
|
void *OpDecl = nullptr,
|
|
bool GlobalRef = true) {
|
|
auto Res = std::make_unique<X86Operand>(Immediate, StartLoc, EndLoc);
|
|
Res->Imm.Val = Val;
|
|
Res->Imm.LocalRef = !GlobalRef;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
Res->AddressOf = true;
|
|
return Res;
|
|
}
|
|
|
|
/// Create an absolute memory operand.
|
|
static std::unique_ptr<X86Operand>
|
|
CreateMem(unsigned ModeSize, const MCExpr *Disp, SMLoc StartLoc, SMLoc EndLoc,
|
|
unsigned Size = 0, StringRef SymName = StringRef(),
|
|
void *OpDecl = nullptr, unsigned FrontendSize = 0,
|
|
bool UseUpRegs = false, bool MaybeDirectBranchDest = true) {
|
|
auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
|
|
Res->Mem.SegReg = 0;
|
|
Res->Mem.Disp = Disp;
|
|
Res->Mem.BaseReg = 0;
|
|
Res->Mem.DefaultBaseReg = 0;
|
|
Res->Mem.IndexReg = 0;
|
|
Res->Mem.Scale = 1;
|
|
Res->Mem.Size = Size;
|
|
Res->Mem.ModeSize = ModeSize;
|
|
Res->Mem.FrontendSize = FrontendSize;
|
|
Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
|
|
Res->UseUpRegs = UseUpRegs;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
Res->AddressOf = false;
|
|
return Res;
|
|
}
|
|
|
|
/// Create a generalized memory operand.
|
|
static std::unique_ptr<X86Operand>
|
|
CreateMem(unsigned ModeSize, unsigned SegReg, const MCExpr *Disp,
|
|
unsigned BaseReg, unsigned IndexReg, unsigned Scale, SMLoc StartLoc,
|
|
SMLoc EndLoc, unsigned Size = 0,
|
|
unsigned DefaultBaseReg = X86::NoRegister,
|
|
StringRef SymName = StringRef(), void *OpDecl = nullptr,
|
|
unsigned FrontendSize = 0, bool UseUpRegs = false,
|
|
bool MaybeDirectBranchDest = true) {
|
|
// We should never just have a displacement, that should be parsed as an
|
|
// absolute memory operand.
|
|
assert((SegReg || BaseReg || IndexReg || DefaultBaseReg) &&
|
|
"Invalid memory operand!");
|
|
|
|
// The scale should always be one of {1,2,4,8}.
|
|
assert(((Scale == 1 || Scale == 2 || Scale == 4 || Scale == 8)) &&
|
|
"Invalid scale!");
|
|
auto Res = std::make_unique<X86Operand>(Memory, StartLoc, EndLoc);
|
|
Res->Mem.SegReg = SegReg;
|
|
Res->Mem.Disp = Disp;
|
|
Res->Mem.BaseReg = BaseReg;
|
|
Res->Mem.DefaultBaseReg = DefaultBaseReg;
|
|
Res->Mem.IndexReg = IndexReg;
|
|
Res->Mem.Scale = Scale;
|
|
Res->Mem.Size = Size;
|
|
Res->Mem.ModeSize = ModeSize;
|
|
Res->Mem.FrontendSize = FrontendSize;
|
|
Res->Mem.MaybeDirectBranchDest = MaybeDirectBranchDest;
|
|
Res->UseUpRegs = UseUpRegs;
|
|
Res->SymName = SymName;
|
|
Res->OpDecl = OpDecl;
|
|
Res->AddressOf = false;
|
|
return Res;
|
|
}
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif // LLVM_LIB_TARGET_X86_ASMPARSER_X86OPERAND_H
|