aa1d2693c2
ShadowCallStack implementation uses s2 register on RISC-V, but that choice is problematic for reasons described in: https://lists.riscv.org/g/sig-toolchains/message/544, https://github.com/riscv-non-isa/riscv-elf-psabi-doc/issues/370, and https://github.com/google/android-riscv64/issues/72 The concern over the register choice was also brought up in https://reviews.llvm.org/D84414. https://reviews.llvm.org/D84414#2228666 said: ``` "If the register choice is the only concern about this work, then I think we can probably land it as-is and fixup the register choice if we see major drawbacks later. Yes, it's an ABI issue, but on the other hand the shadow call stack is not a standard ABI anyway."" ``` Since we have now found a sufficient reason to fixup the register choice, we should go ahead and update the implementation. We propose using x3(gp) which is now the platform register in the RISC-V ABI. Reviewed By: asb, hiraditya, mcgrathr, craig.topper Differential Revision: https://reviews.llvm.org/D146463
90 lines
2.9 KiB
C++
90 lines
2.9 KiB
C++
//===-- RISCVTargetParser.cpp - Parser for target features ------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements a target parser to recognise hardware features
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// for RISC-V CPUs.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/TargetParser/RISCVTargetParser.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/TargetParser/Triple.h"
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namespace llvm {
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namespace RISCV {
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struct CPUInfo {
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StringLiteral Name;
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CPUKind Kind;
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StringLiteral DefaultMarch;
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bool isInvalid() const { return DefaultMarch.empty(); }
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bool is64Bit() const { return DefaultMarch.starts_with("rv64"); }
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};
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constexpr CPUInfo RISCVCPUInfo[] = {
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#define PROC(ENUM, NAME, DEFAULT_MARCH) \
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{NAME, CK_##ENUM, DEFAULT_MARCH},
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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};
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bool checkCPUKind(CPUKind Kind, bool IsRV64) {
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if (Kind == CK_INVALID)
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return false;
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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bool checkTuneCPUKind(CPUKind Kind, bool IsRV64) {
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if (Kind == CK_INVALID)
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return false;
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#define TUNE_PROC(ENUM, NAME) \
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if (Kind == CK_##ENUM) \
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return true;
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].is64Bit() == IsRV64;
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}
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CPUKind parseCPUKind(StringRef CPU) {
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return llvm::StringSwitch<CPUKind>(CPU)
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#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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.Default(CK_INVALID);
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}
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CPUKind parseTuneCPUKind(StringRef TuneCPU, bool IsRV64) {
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return llvm::StringSwitch<CPUKind>(TuneCPU)
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#define PROC(ENUM, NAME, DEFAULT_MARCH) .Case(NAME, CK_##ENUM)
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#define TUNE_PROC(ENUM, NAME) .Case(NAME, CK_##ENUM)
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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.Default(CK_INVALID);
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}
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StringRef getMArchFromMcpu(StringRef CPU) {
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CPUKind Kind = parseCPUKind(CPU);
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return RISCVCPUInfo[static_cast<unsigned>(Kind)].DefaultMarch;
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}
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void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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}
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void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64) {
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for (const auto &C : RISCVCPUInfo) {
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if (C.Kind != CK_INVALID && IsRV64 == C.is64Bit())
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Values.emplace_back(C.Name);
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}
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#define TUNE_PROC(ENUM, NAME) Values.emplace_back(StringRef(NAME));
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#include "llvm/TargetParser/RISCVTargetParserDef.inc"
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}
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} // namespace RISCV
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} // namespace llvm
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