b4e1b0e00d
Each dead def of the same virtual register is required to be split into multiple virtual registers with separate live intervals to avoid MachineVerifier error. Partially fixes https://github.com/llvm/llvm-project/issues/56050 and https://github.com/llvm/llvm-project/issues/56051 Reviewed By: qcolombet Differential Revision: https://reviews.llvm.org/D130477
35 lines
1.3 KiB
YAML
35 lines
1.3 KiB
YAML
# REQUIRES: asserts
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# RUN: llc -mcpu=cortex-a57 -mtriple=thumb -enable-misched -run-pass=machine-scheduler -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
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# CHECK-LABEL: ********** MI Scheduling **********
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# CHECK: %[[RES:[0-9]+]]:rgpr = t2MLA
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# CHECK-NEXT: # preds left
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# CHECK-NEXT: # succs left
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# CHECK-NEXT: # rdefs left
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# CHECK-NEXT: Latency : 3
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# CHECK-NEXT: Depth
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# CHECK-NEXT: Height
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# CHECK-NEXT: Predecessors:
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# CHECK-NEXT: SU({{.*}}): Data Latency=1 Reg=
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# CHECK-NEXT: SU({{.*}}): Data Latency=1 Reg=
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# CHECK-NEXT: Successors:
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# CHECK-NEXT: SU([[SMLA_SU:[0-9]+]]): Data Latency=1 Reg=%[[RES]]
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# CHECK-NEXT: Pressure Diff
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# CHECK-NEXT: Single Issue : false;
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# CHECK-NEXT: SU([[SMLA_SU]]): {{.*}} = t2SMLAL %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr, %{{[0-9]+}}:rgpr(tied-def 0), %[[RES]]:rgpr(tied-def 1), 14, $noreg
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name: test_smlal_forwarding
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $r1, $r3, $r4, $r5, $r6
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%1:rgpr = COPY $r1
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%3:rgpr = COPY $r3
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%4:rgpr = COPY $r4
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%5:rgpr = COPY $r5
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%6:rgpr = COPY $r6
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%3:rgpr = t2MLA %4:rgpr, %1:rgpr, %4:rgpr, 14, $noreg
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%6:rgpr, %5:rgpr = t2SMLAL %5:rgpr, %6:rgpr, %4:rgpr, %3:rgpr, 14, $noreg
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$r0 = COPY %6:rgpr
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BX_RET 14, $noreg, implicit $r0
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