ee4ba9f3a1
Unfortunately, it seems we really do need to take the long route; start from the "merge" block, find (all the) "dispatch" blocks, and deal with each "dispatch" block separately, instead of simply starting from each "dispatch" block like it would logically make sense, otherwise we run into a number of other missing folds around `switch` formation, missing sinking/hoisting and phase ordering. This reverts commit 85628ce75b3084dc0f185a320152baf85b59aba7. This reverts commit c5fff9095342a792bf4b9a077fe3c3a83c4e566c. This reverts commit 34a98e1046e3aa55e5f26ab20a15e96b4034d25a. This reverts commit 1e353f092288309d74d380367aa50bbd383780ed.
32 lines
839 B
LLVM
32 lines
839 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s -check-prefix=A8
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; RUN: llc -mtriple=arm-eabi -mcpu=swift %s -o - | FileCheck %s -check-prefix=SWIFT
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define i32 @t1(i32 %a, i32 %b) {
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; A8-LABEL: t1:
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; A8: @ %bb.0: @ %common.ret
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; A8-NEXT: mov r2, #1
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; A8-NEXT: cmp r0, #0
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; A8-NEXT: mvneq r2, #0
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; A8-NEXT: add r0, r1, r2
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; A8-NEXT: bx lr
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;
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; SWIFT-LABEL: t1:
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; SWIFT: @ %bb.0: @ %common.ret
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; SWIFT-NEXT: mov r2, #1
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; SWIFT-NEXT: cmp r0, #0
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; SWIFT-NEXT: mvneq r2, #0
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; SWIFT-NEXT: add r0, r1, r2
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; SWIFT-NEXT: bx lr
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%tmp2 = icmp eq i32 %a, 0
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br i1 %tmp2, label %cond_false, label %cond_true
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cond_true:
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%tmp5 = add i32 %b, 1
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ret i32 %tmp5
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cond_false:
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%tmp7 = add i32 %b, -1
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ret i32 %tmp7
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}
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