7863cc6c1c
The fix applied in D23303 "LiveIntervalAnalysis: fix a crash in repairOldRegInRange" was over-zealous. It would bail out when the end of the range to be repaired was in the middle of the first segment of the live range of Reg, which was always the case when the range contained a single def of Reg. This patch fixes it as suggested by Matthias Braun in post-commit review on the original patch, and tests it by adding -early-live-intervals to a selection of existing lit tests that now pass. (Note that D23303 was originally applied to fix a crash in SILoadStoreOptimizer, but that is now moot since D23814 updated SILoadStoreOptimizer to run before scheduling so it no longer has to update live intervals.) Differential Revision: https://reviews.llvm.org/D110238 Unrevert with some changes to the tests: - Add -verify-machineinstrs to check for remaining problems in live interval support in TwoAddressInstructionPass. - Drop test/CodeGen/AMDGPU/extract-load-i1.ll since it suffers from some of those remaining problems.
19 lines
701 B
LLVM
19 lines
701 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=armv8 | FileCheck %s
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; RUN: llc < %s -mtriple=armv8 -early-live-intervals -verify-machineinstrs | FileCheck %s
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define <4 x i32> @test(<4 x i32> %m) {
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; CHECK-LABEL: test:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov d17, r2, r3
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; CHECK-NEXT: vmov d16, r0, r1
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; CHECK-NEXT: vshl.i32 q8, q8, #24
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; CHECK-NEXT: vshr.s32 q8, q8, #24
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; CHECK-NEXT: vmov r0, r1, d16
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; CHECK-NEXT: vmov r2, r3, d17
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; CHECK-NEXT: bx lr
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entry:
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%shl = shl <4 x i32> %m, <i32 24, i32 24, i32 24, i32 24>
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%shr = ashr exact <4 x i32> %shl, <i32 24, i32 24, i32 24, i32 24>
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ret <4 x i32> %shr
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}
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