0408b131eb
Integer legalization already supported splitting the output integer of
llround and llrint, but did not support this for lround and lrint yet.
This is not a problem for 32-bit architectures, but for 8/16-bit
architectures like AVR it results in a crash like this:
ExpandIntegerResult #0: t7: i32 = lround t6
LLVM ERROR: Do not know how to expand the result of this operator!
This patch simply add lrint/lround to the list of ISD opcodes to expand.
Fixes https://github.com/llvm/llvm-project/issues/59573.
Differential Revision: https://reviews.llvm.org/D140822
52 lines
1.3 KiB
LLVM
52 lines
1.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=avr -mcpu=atmega328p | FileCheck %s
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define signext i32 @testmsws(float %x) {
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; CHECK-LABEL: testmsws:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call llroundf
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; CHECK-NEXT: movw r22, r18
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; CHECK-NEXT: movw r24, r20
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llround.i64.f32(float %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxs(float %x) {
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; CHECK-LABEL: testmsxs:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call llroundf
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llround.i64.f32(float %x)
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ret i64 %0
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}
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define signext i32 @testmswd(double %x) {
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; CHECK-LABEL: testmswd:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call llround
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; CHECK-NEXT: movw r22, r18
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; CHECK-NEXT: movw r24, r20
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llround.i64.f64(double %x)
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%conv = trunc i64 %0 to i32
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ret i32 %conv
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}
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define i64 @testmsxd(double %x) {
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; CHECK-LABEL: testmsxd:
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; CHECK: ; %bb.0: ; %entry
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; CHECK-NEXT: call llround
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; CHECK-NEXT: ret
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entry:
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%0 = tail call i64 @llvm.llround.i64.f64(double %x)
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ret i64 %0
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}
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declare i64 @llvm.llround.i64.f32(float) nounwind readnone
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declare i64 @llvm.llround.i64.f64(double) nounwind readnone
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