2224b53f06
Summary: Some 64 bit constants can be materialized with fewer instructions than we currently use. We consider a 64 bit immediate value divided into four parts, Hi16OfHi32 (bits 48...63), Lo16OfHi32 (bits 32...47), Hi16OfLo32 (bits 16...31), Lo16OfLo32 (bits 0...15). When any three parts are equal, the immediate can be treated as "almost" a splat of a 32 bit value in a 64 bit register. For such case, we can use 3 instructions to generate the splat and use 1 instruction to modify the different part: Reviewed By: shchenz Differential Revision: https://reviews.llvm.org/D139813
428 lines
8.9 KiB
LLVM
428 lines
8.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -mtriple powerpc64-unknown-linux-gnu -mcpu=ppc64 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -vec-extabi -mcpu=ppc64 < %s | FileCheck %s
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; Function Attrs: nounwind readnone
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define i64 @cn1() #0 {
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; CHECK-LABEL: cn1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 0, 16
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; CHECK-NEXT: blr
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entry:
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ret i64 281474976710655
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}
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; Function Attrs: nounwind readnone
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define i64 @cnb() #0 {
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; CHECK-LABEL: cnb:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -81
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; CHECK-NEXT: rldic 3, 3, 0, 16
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; CHECK-NEXT: blr
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entry:
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ret i64 281474976710575
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}
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; Function Attrs: nounwind readnone
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define i64 @f2(i64 %x) #0 {
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; CHECK-LABEL: f2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 36, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 -68719476736
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}
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; Function Attrs: nounwind readnone
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define i64 @f2a(i64 %x) #0 {
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; CHECK-LABEL: f2a:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -337
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; CHECK-NEXT: rldic 3, 3, 30, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 -361850994688
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}
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; Function Attrs: nounwind readnone
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define i64 @f2n(i64 %x) #0 {
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; CHECK-LABEL: f2n:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 0, 28
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; CHECK-NEXT: blr
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entry:
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ret i64 68719476735
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}
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; Function Attrs: nounwind readnone
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define i64 @f3(i64 %x) #0 {
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; CHECK-LABEL: f3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 0, 31
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; CHECK-NEXT: blr
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entry:
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ret i64 8589934591
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}
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; Function Attrs: nounwind readnone
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define i64 @cn2n() #0 {
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; CHECK-LABEL: cn2n:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -5121
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; CHECK-NEXT: ori 3, 3, 65534
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; CHECK-NEXT: rotldi 3, 3, 22
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; CHECK-NEXT: blr
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entry:
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ret i64 -1407374887747585
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}
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define i64 @uint32_1() #0 {
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; CHECK-LABEL: uint32_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 18176
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; CHECK-NEXT: oris 3, 3, 59509
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; CHECK-NEXT: blr
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entry:
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ret i64 3900000000
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}
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define i32 @uint32_1_i32() #0 {
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; CHECK-LABEL: uint32_1_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 18176
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; CHECK-NEXT: oris 3, 3, 59509
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; CHECK-NEXT: blr
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entry:
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ret i32 -394967296
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}
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define i64 @uint32_2() #0 {
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; CHECK-LABEL: uint32_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 0, 32
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; CHECK-NEXT: blr
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entry:
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ret i64 4294967295
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}
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define i32 @uint32_2_i32() #0 {
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; CHECK-LABEL: uint32_2_i32:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -1
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; CHECK-NEXT: rldic 3, 3, 0, 32
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; CHECK-NEXT: blr
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entry:
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ret i32 -1
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}
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define i64 @uint32_3() #0 {
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; CHECK-LABEL: uint32_3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: rldic 3, 3, 31, 32
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; CHECK-NEXT: blr
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entry:
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ret i64 2147483648
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}
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define i64 @uint32_4() #0 {
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; CHECK-LABEL: uint32_4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -6027
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; CHECK-NEXT: ori 3, 3, 18177
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; CHECK-NEXT: rldic 3, 3, 5, 27
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; CHECK-NEXT: blr
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entry:
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ret i64 124800000032
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}
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define i64 @cn_ones_1() #0 {
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; CHECK-LABEL: cn_ones_1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -25633
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; CHECK-NEXT: rldicl 3, 3, 18, 30
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; CHECK-NEXT: blr
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entry:
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ret i64 10460594175
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}
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define i64 @cn_ones_2() #0 {
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; CHECK-LABEL: cn_ones_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -25638
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; CHECK-NEXT: ori 3, 3, 24575
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; CHECK-NEXT: rldicl 3, 3, 2, 30
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; CHECK-NEXT: blr
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entry:
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ret i64 10459119615
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}
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define i64 @imm1() #0 {
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; CHECK-LABEL: imm1:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 8465
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; CHECK-NEXT: rldic 3, 3, 28, 22
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; CHECK-NEXT: blr
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entry:
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ret i64 2272306135040 ;0x21110000000
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}
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define i64 @imm2() #0 {
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; CHECK-LABEL: imm2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -28536
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; CHECK-NEXT: rldicl 3, 3, 1, 32
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; CHECK-NEXT: blr
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entry:
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ret i64 4294910225 ;0xFFFF2111
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}
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define i64 @imm3() #0 {
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; CHECK-LABEL: imm3:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -32495
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; CHECK-NEXT: rldic 3, 3, 0, 32
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; CHECK-NEXT: blr
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entry:
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ret i64 4294934801 ;0xFFFF8111
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}
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define i64 @imm4() #0 {
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; CHECK-LABEL: imm4:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, 33
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; CHECK-NEXT: ori 3, 3, 4352
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; CHECK-NEXT: rldimi 3, 3, 32, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 9307365931290880 ;0x21110000211100
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}
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define i64 @imm5() #0 {
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; CHECK-LABEL: imm5:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 28685
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; CHECK-NEXT: rotldi 3, 3, 52
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; CHECK-NEXT: blr
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entry:
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ret i64 58546795155816455 ;0xd0000000000007
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}
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define i64 @imm6() #0 {
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; CHECK-LABEL: imm6:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -1
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; CHECK-NEXT: ori 3, 3, 28674
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; CHECK-NEXT: rotldi 3, 3, 52
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; CHECK-NEXT: blr
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entry:
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ret i64 13510798882111479 ;0x2ffffffffffff7
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}
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define i64 @imm7() #0 {
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; CHECK-LABEL: imm7:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -3823
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; CHECK-NEXT: rldic 3, 3, 28, 20
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; CHECK-NEXT: blr
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entry:
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ret i64 16565957296128 ;0xf1110000000
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}
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define i64 @imm8() #0 {
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; CHECK-LABEL: imm8:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -7919
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; CHECK-NEXT: rldic 3, 3, 22, 22
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; CHECK-NEXT: blr
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entry:
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ret i64 4364831817728 ;0x3f844400000
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}
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define i64 @imm9() #0 {
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; CHECK-LABEL: imm9:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -1
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; CHECK-NEXT: ori 3, 3, 28674
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; CHECK-NEXT: rotldi 3, 3, 52
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; CHECK-NEXT: blr
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entry:
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ret i64 13510798882111479 ;0x2ffffffffffff7
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}
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define i64 @imm10() #0 {
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; CHECK-LABEL: imm10:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -3823
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; CHECK-NEXT: rldic 3, 3, 28, 20
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; CHECK-NEXT: blr
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entry:
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ret i64 16565957296128 ;0xf1110000000
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}
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define i64 @imm11() #0 {
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; CHECK-LABEL: imm11:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -7919
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; CHECK-NEXT: rldic 3, 3, 22, 22
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; CHECK-NEXT: blr
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entry:
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ret i64 4364831817728 ;0x3f844400000
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}
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define i64 @imm12() #0 {
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; CHECK-LABEL: imm12:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -29
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; CHECK-NEXT: ori 3, 3, 64577
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; CHECK-NEXT: rldic 3, 3, 12, 20
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; CHECK-NEXT: blr
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entry:
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ret i64 17584665923584 ;0xffe3fc41000
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}
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define i64 @imm13() #0 {
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; CHECK-LABEL: imm13:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -24847
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; CHECK-NEXT: rldicl 3, 3, 21, 27
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; CHECK-NEXT: blr
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entry:
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ret i64 85333114879 ;0x13de3fffff
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}
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define i64 @imm13_2() #0 {
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; CHECK-LABEL: imm13_2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -12424
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; CHECK-NEXT: rldicl 3, 3, 22, 26
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; CHECK-NEXT: blr
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entry:
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ret i64 222772068351 ;0x33de3fffff
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}
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define i64 @imm14() #0 {
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; CHECK-LABEL: imm14:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -3960
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; CHECK-NEXT: rldicl 3, 3, 21, 24
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; CHECK-NEXT: blr
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entry:
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ret i64 1091209003007 ;0xfe111fffff
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}
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define i64 @imm15() #0 {
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; CHECK-LABEL: imm15:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, -8065
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; CHECK-NEXT: rldic 3, 3, 24, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 -135308247040
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}
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define i64 @imm16() #0 {
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; CHECK-LABEL: imm16:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -16392
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; CHECK-NEXT: ori 3, 3, 57217
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; CHECK-NEXT: rldic 3, 3, 16, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 -70399354142720
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}
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define i64 @imm17() #0 {
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; CHECK-LABEL: imm17:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, 20344
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; CHECK-NEXT: ori 3, 3, 32847
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; CHECK-NEXT: rotldi 3, 3, 49
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; CHECK-NEXT: blr
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entry:
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ret i64 44473046320324337 ;0x9e000000009ef1
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}
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define i64 @imm18() #0 {
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; CHECK-LABEL: imm18:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: li 3, 1
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; CHECK-NEXT: rldic 3, 3, 33, 30
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; CHECK-NEXT: oris 3, 3, 39436
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; CHECK-NEXT: ori 3, 3, 61633
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; CHECK-NEXT: blr
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entry:
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ret i64 11174473921
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}
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define i64 @imm19() {
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; CHECK-LABEL: imm19:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -13105
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; CHECK-NEXT: ori 3, 3, 52479
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; CHECK-NEXT: rldic 3, 3, 32, 0
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; CHECK-NEXT: oris 3, 3, 52431
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; CHECK-NEXT: ori 3, 3, 291
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; CHECK-NEXT: blr
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entry:
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ret i64 14758239902941249827 ;0xCCCFCCFFCCCF0123
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}
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define i64 @imm20() {
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; CHECK-LABEL: imm20:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, 291
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; CHECK-NEXT: ori 3, 3, 52479
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; CHECK-NEXT: rldimi 3, 3, 32, 0
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; CHECK-NEXT: rldimi 3, 3, 48, 0
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; CHECK-NEXT: blr
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entry:
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ret i64 14771750698406366463 ;0xCCFFCCFF0123CCFF
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}
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define i64 @imm21() {
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; CHECK-LABEL: imm21:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, -13057
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; CHECK-NEXT: ori 3, 3, 291
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; CHECK-NEXT: rldimi 3, 3, 32, 0
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; CHECK-NEXT: rlwimi 3, 3, 16, 16, 31
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; CHECK-NEXT: blr
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entry:
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ret i64 14771526556073315583 ;0xCCFF0123CCFFCCFF
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}
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define i64 @imm22() {
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; CHECK-LABEL: imm22:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: lis 3, 291
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; CHECK-NEXT: ori 3, 3, 52479
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; CHECK-NEXT: rldimi 3, 3, 32, 0
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; CHECK-NEXT: rlwimi 3, 3, 16, 0, 15
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; CHECK-NEXT: blr
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entry:
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ret i64 82134617250843903 ;0x0123CCFFCCFFCCFF
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}
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attributes #0 = { nounwind readnone }
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