eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
121 lines
3.8 KiB
LLVM
121 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -o - \
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; RUN: -ppc-asm-full-reg-names -verify-machineinstrs %s | FileCheck %s
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; Function Attrs: nounwind
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define dso_local zeroext i32 @test(i32 signext %l) nounwind {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: stdu r1, -32(r1)
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; CHECK-NEXT: addi r3, r3, -1
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; CHECK-NEXT: std r0, 48(r1)
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; CHECK-NEXT: cmplwi r3, 5
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; CHECK-NEXT: bgt cr0, .LBB0_3
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; CHECK-NEXT: # %bb.1: # %entry
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; CHECK-NEXT: addis r4, r2, .LC0@toc@ha
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; CHECK-NEXT: rldic r3, r3, 2, 30
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; CHECK-NEXT: ld r4, .LC0@toc@l(r4)
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; CHECK-NEXT: lwax r3, r3, r4
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; CHECK-NEXT: add r3, r3, r4
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; CHECK-NEXT: mtctr r3
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; CHECK-NEXT: bctr
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; CHECK-NEXT: .LBB0_2: # %sw.bb
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; CHECK-NEXT: li r3, 2
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; CHECK-NEXT: bl test1
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_10
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; CHECK-NEXT: .LBB0_3: # %sw.default
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; CHECK-NEXT: li r3, 1
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; CHECK-NEXT: bl test1
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test3
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_10
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; CHECK-NEXT: .LBB0_4: # %sw.bb3
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; CHECK-NEXT: li r3, 3
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; CHECK-NEXT: b .LBB0_9
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; CHECK-NEXT: .LBB0_5: # %sw.bb5
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; CHECK-NEXT: li r3, 4
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; CHECK-NEXT: bl test2
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test3
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_10
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; CHECK-NEXT: .LBB0_6: # %sw.bb8
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; CHECK-NEXT: li r3, 5
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; CHECK-NEXT: bl test4
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_10
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; CHECK-NEXT: .LBB0_7: # %sw.bb10
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; CHECK-NEXT: li r3, 66
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; CHECK-NEXT: bl test4
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test1
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; CHECK-NEXT: nop
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; CHECK-NEXT: b .LBB0_10
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; CHECK-NEXT: .LBB0_8: # %sw.bb13
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; CHECK-NEXT: li r3, 66
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; CHECK-NEXT: .LBB0_9: # %return
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; CHECK-NEXT: bl test2
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; CHECK-NEXT: nop
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; CHECK-NEXT: .LBB0_10: # %return
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; CHECK-NEXT: clrldi r3, r3, 32
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; CHECK-NEXT: addi r1, r1, 32
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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entry:
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switch i32 %l, label %sw.default [
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i32 1, label %sw.bb
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i32 2, label %sw.bb3
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i32 3, label %sw.bb5
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i32 4, label %sw.bb8
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i32 5, label %sw.bb10
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i32 6, label %sw.bb13
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]
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sw.default: ; preds = %entry
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%call = tail call signext i32 @test1(i32 signext 1)
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%call1 = tail call signext i32 @test3(i32 signext %call)
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br label %return
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sw.bb: ; preds = %entry
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%call2 = tail call signext i32 @test1(i32 signext 2)
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br label %return
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sw.bb3: ; preds = %entry
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%call4 = tail call signext i32 @test2(i32 signext 3)
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br label %return
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sw.bb5: ; preds = %entry
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%call6 = tail call signext i32 @test2(i32 signext 4)
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%call7 = tail call signext i32 @test3(i32 signext %call6)
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br label %return
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sw.bb8: ; preds = %entry
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%call9 = tail call signext i32 @test4(i32 signext 5)
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br label %return
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sw.bb10: ; preds = %entry
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%call11 = tail call signext i32 @test4(i32 signext 66)
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%call12 = tail call signext i32 @test1(i32 signext %call11)
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br label %return
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sw.bb13: ; preds = %entry
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%call14 = tail call signext i32 @test2(i32 signext 66)
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br label %return
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return: ; preds = %sw.bb13, %sw.bb10, %sw.bb8, %sw.bb5, %sw.bb3, %sw.bb, %sw.default
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%retval.0 = phi i32 [ %call1, %sw.default ], [ %call14, %sw.bb13 ], [ %call12, %sw.bb10 ], [ %call9, %sw.bb8 ], [ %call7, %sw.bb5 ], [ %call4, %sw.bb3 ], [ %call2, %sw.bb ]
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ret i32 %retval.0
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}
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declare signext i32 @test3(i32 signext)
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declare signext i32 @test1(i32 signext)
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declare signext i32 @test2(i32 signext)
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declare signext i32 @test4(i32 signext)
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