eb7d16ea25
mflr is kind of expensive on Power version smaller than 10, so we should schedule the store for the mflr's def away from mflr. In epilogue, the expensive mtlr has no user for its def, so it doesn't matter that the load and the mtlr are back-to-back. Reviewed By: RolandF Differential Revision: https://reviews.llvm.org/D137423
222 lines
5.7 KiB
LLVM
222 lines
5.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -relocation-model=pic -verify-machineinstrs -mcpu=pwr7 -mattr=+altivec -mattr=-vsx < %s | FileCheck %s
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target datalayout = "e-m:e-i64:64-n32:64"
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target triple = "powerpc64le-unknown-linux-gnu"
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@g = common global ppc_fp128 0xM00000000000000000000000000000000, align 16
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define void @callee(ppc_fp128 %x) {
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; CHECK-LABEL: callee:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: stfd 2, -8(1)
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; CHECK-NEXT: stfd 1, -16(1)
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: stfd 2, 8(3)
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; CHECK-NEXT: stfd 1, 0(3)
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; CHECK-NEXT: blr
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entry:
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%x.addr = alloca ppc_fp128, align 16
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store ppc_fp128 %x, ptr %x.addr, align 16
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%0 = load ppc_fp128, ptr %x.addr, align 16
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store ppc_fp128 %0, ptr @g, align 16
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ret void
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}
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define void @caller() {
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; CHECK-LABEL: caller:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -32(1)
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; CHECK-NEXT: std 0, 48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: lfd 2, 8(3)
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; CHECK-NEXT: lfd 1, 0(3)
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; CHECK-NEXT: bl test
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%0 = load ppc_fp128, ptr @g, align 16
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call void @test(ppc_fp128 %0)
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ret void
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}
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declare void @test(ppc_fp128)
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define void @caller_const() {
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; CHECK-LABEL: caller_const:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -32(1)
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; CHECK-NEXT: std 0, 48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: addis 3, 2, .LCPI2_0@toc@ha
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; CHECK-NEXT: addis 4, 2, .LCPI2_1@toc@ha
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; CHECK-NEXT: lfs 1, .LCPI2_0@toc@l(3)
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; CHECK-NEXT: lfs 2, .LCPI2_1@toc@l(4)
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; CHECK-NEXT: bl test
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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call void @test(ppc_fp128 0xM3FF00000000000000000000000000000)
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ret void
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}
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define ppc_fp128 @result() {
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; CHECK-LABEL: result:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: lfd 1, 0(3)
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; CHECK-NEXT: lfd 2, 8(3)
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; CHECK-NEXT: blr
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entry:
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%0 = load ppc_fp128, ptr @g, align 16
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ret ppc_fp128 %0
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}
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define void @use_result() {
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; CHECK-LABEL: use_result:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -32(1)
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; CHECK-NEXT: std 0, 48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl test_result
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; CHECK-NEXT: nop
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; CHECK-NEXT: addis 3, 2, .LC0@toc@ha
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; CHECK-NEXT: ld 3, .LC0@toc@l(3)
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; CHECK-NEXT: stfd 2, 8(3)
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; CHECK-NEXT: stfd 1, 0(3)
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%call = tail call ppc_fp128 @test_result() #3
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store ppc_fp128 %call, ptr @g, align 16
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ret void
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}
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declare ppc_fp128 @test_result()
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define void @caller_result() {
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; CHECK-LABEL: caller_result:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: mflr 0
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; CHECK-NEXT: stdu 1, -32(1)
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; CHECK-NEXT: std 0, 48(1)
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; CHECK-NEXT: .cfi_def_cfa_offset 32
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: bl test_result
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; CHECK-NEXT: nop
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; CHECK-NEXT: bl test
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi 1, 1, 32
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; CHECK-NEXT: ld 0, 16(1)
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; CHECK-NEXT: mtlr 0
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; CHECK-NEXT: blr
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entry:
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%call = tail call ppc_fp128 @test_result()
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tail call void @test(ppc_fp128 %call)
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ret void
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}
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define i128 @convert_from(ppc_fp128 %x) {
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; CHECK-LABEL: convert_from:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: stfd 1, -16(1)
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; CHECK-NEXT: stfd 2, -8(1)
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; CHECK-NEXT: ld 3, -16(1)
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; CHECK-NEXT: ld 4, -8(1)
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; CHECK-NEXT: blr
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entry:
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%0 = bitcast ppc_fp128 %x to i128
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ret i128 %0
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}
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define ppc_fp128 @convert_to(i128 %x) {
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; CHECK-LABEL: convert_to:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: std 3, -16(1)
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; CHECK-NEXT: std 4, -8(1)
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; CHECK-NEXT: lfd 1, -16(1)
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; CHECK-NEXT: lfd 2, -8(1)
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; CHECK-NEXT: blr
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entry:
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%0 = bitcast i128 %x to ppc_fp128
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ret ppc_fp128 %0
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}
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define ppc_fp128 @convert_to2(i128 %x) {
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; CHECK-LABEL: convert_to2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: rotldi 5, 3, 1
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; CHECK-NEXT: sldi 3, 3, 1
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; CHECK-NEXT: rldimi 5, 4, 1, 0
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; CHECK-NEXT: std 3, -16(1)
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; CHECK-NEXT: std 5, -8(1)
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; CHECK-NEXT: lfd 1, -16(1)
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; CHECK-NEXT: lfd 2, -8(1)
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; CHECK-NEXT: blr
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entry:
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%shl = shl i128 %x, 1
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%0 = bitcast i128 %shl to ppc_fp128
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ret ppc_fp128 %0
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}
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define double @convert_vector(<4 x i32> %x) {
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; CHECK-LABEL: convert_vector:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi 3, 1, -16
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; CHECK-NEXT: stvx 2, 0, 3
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; CHECK-NEXT: lfd 1, -16(1)
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; CHECK-NEXT: blr
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entry:
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%cast = bitcast <4 x i32> %x to ppc_fp128
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%conv = fptrunc ppc_fp128 %cast to double
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ret double %conv
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}
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declare void @llvm.va_start(ptr)
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define double @vararg(i32 %a, ...) {
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; CHECK-LABEL: vararg:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi 3, 1, 55
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; CHECK-NEXT: std 4, 40(1)
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; CHECK-NEXT: rldicr 3, 3, 0, 59
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; CHECK-NEXT: std 5, 48(1)
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; CHECK-NEXT: ori 4, 3, 8
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; CHECK-NEXT: std 6, 56(1)
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; CHECK-NEXT: std 7, 64(1)
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; CHECK-NEXT: std 8, 72(1)
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; CHECK-NEXT: std 9, 80(1)
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; CHECK-NEXT: std 10, 88(1)
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; CHECK-NEXT: std 4, -8(1)
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; CHECK-NEXT: lfd 1, 0(3)
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; CHECK-NEXT: addi 3, 3, 16
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; CHECK-NEXT: std 3, -8(1)
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; CHECK-NEXT: blr
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entry:
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%va = alloca ptr, align 8
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call void @llvm.va_start(ptr %va)
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%arg = va_arg ptr %va, ppc_fp128
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%conv = fptrunc ppc_fp128 %arg to double
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ret double %conv
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}
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