8f891b7c39
createInductionResumeValues creates a phi node placeholder without filling incoming values. Then it generates the incoming values. It includes triggering of SCEV expander which may invoke SSAUpdater. SSAUpdater has an optimization to detect number of predecessors basing on incoming values if there is phi node. In case phi node is not filled with incoming values - the number of predecessors is detected as 0 and this leads to segmentation fault. In other words SSAUpdater expects that phi is in good shape while LoopVectorizer breaks this requirement. The fix is just prepare all incoming values first and then build a phi node. Reviewed By: fhahn Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D128033
114 lines
6.0 KiB
LLVM
114 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -S -passes=loop-vectorize < %s | FileCheck %s
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; This is a regression test. Without the fix it crashes on SSAUpdater due to
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; LoopVectroizer created a phi node placeholder without incoming values but
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; SSAUpdater expects that phi node is completely filled.
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target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128-ni:1-p2:32:8:8:32-ni:2"
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define void @test(i32 %arg, i32 %L1.limit, i32 %L2.switch, i1 %c) {
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; CHECK-LABEL: @test(
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; CHECK-NEXT: L1.preheader:
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; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -1, [[ARG:%.*]]
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; CHECK-NEXT: br label [[L1_HEADER:%.*]]
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; CHECK: L1.header:
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; CHECK-NEXT: [[INDUCTION_IV:%.*]] = phi i32 [ [[INDUCTION_IV_NEXT:%.*]], [[L1_BACKEDGE:%.*]] ], [ [[TMP0]], [[L1_PREHEADER:%.*]] ]
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; CHECK-NEXT: [[INDVAR:%.*]] = phi i32 [ [[INDVAR_NEXT:%.*]], [[L1_BACKEDGE]] ], [ 0, [[L1_PREHEADER]] ]
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; CHECK-NEXT: [[L1_SUM:%.*]] = phi i32 [ [[ARG]], [[L1_PREHEADER]] ], [ [[L1_SUM_NEXT:%.*]], [[L1_BACKEDGE]] ]
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; CHECK-NEXT: [[L1_IV:%.*]] = phi i32 [ 1, [[L1_PREHEADER]] ], [ [[L1_IV_NEXT:%.*]], [[L1_BACKEDGE]] ]
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; CHECK-NEXT: [[TMP1:%.*]] = mul nsw i32 [[INDVAR]], -1
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; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP1]], -2
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; CHECK-NEXT: br i1 [[C:%.*]], label [[L1_BACKEDGE]], label [[L1_EARLY_EXIT:%.*]]
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; CHECK: L1.backedge:
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; CHECK-NEXT: [[L1_SUM_NEXT]] = add i32 [[L1_IV]], [[L1_SUM]]
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; CHECK-NEXT: [[L1_IV_NEXT]] = add nuw nsw i32 [[L1_IV]], 1
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; CHECK-NEXT: [[L1_EXIT_COND:%.*]] = icmp ult i32 [[L1_IV_NEXT]], [[L1_LIMIT:%.*]]
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; CHECK-NEXT: [[INDVAR_NEXT]] = add i32 [[INDVAR]], 1
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; CHECK-NEXT: [[INDUCTION_IV_NEXT]] = add i32 [[INDUCTION_IV]], [[TMP2]]
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; CHECK-NEXT: br i1 [[L1_EXIT_COND]], label [[L1_HEADER]], label [[L1_EXIT:%.*]]
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; CHECK: L1.early.exit:
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; CHECK-NEXT: ret void
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; CHECK: L1.exit:
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; CHECK-NEXT: [[INDUCTION_IV_LCSSA3:%.*]] = phi i32 [ [[INDUCTION_IV]], [[L1_BACKEDGE]] ]
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; CHECK-NEXT: [[INDUCTION_IV_LCSSA1:%.*]] = phi i32 [ [[INDUCTION_IV]], [[L1_BACKEDGE]] ]
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; CHECK-NEXT: [[L1_EXIT_VAL:%.*]] = phi i32 [ [[L1_SUM_NEXT]], [[L1_BACKEDGE]] ]
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; CHECK-NEXT: br label [[L2_HEADER:%.*]]
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; CHECK: L2.header.loopexit:
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; CHECK-NEXT: br label [[L2_HEADER_BACKEDGE:%.*]]
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; CHECK: L2.header:
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; CHECK-NEXT: switch i32 [[L2_SWITCH:%.*]], label [[L2_HEADER_BACKEDGE]] [
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; CHECK-NEXT: i32 8, label [[L2_EXIT:%.*]]
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; CHECK-NEXT: i32 20, label [[L2_INNER_HEADER_PREHEADER:%.*]]
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; CHECK-NEXT: ]
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; CHECK: L2.header.backedge:
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; CHECK-NEXT: br label [[L2_HEADER]]
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; CHECK: L2.Inner.header.preheader:
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[TMP3:%.*]] = mul i32 12, [[INDUCTION_IV_LCSSA1]]
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; CHECK-NEXT: [[IND_END:%.*]] = add i32 1, [[TMP3]]
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 12
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; CHECK-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 12, 12
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; CHECK-NEXT: br i1 [[CMP_N]], label [[L2_HEADER_LOOPEXIT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 1, [[L2_INNER_HEADER_PREHEADER]] ]
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; CHECK-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ 13, [[MIDDLE_BLOCK]] ], [ 1, [[L2_INNER_HEADER_PREHEADER]] ]
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; CHECK-NEXT: br label [[L2_INNER_HEADER:%.*]]
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; CHECK: L2.Inner.header:
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; CHECK-NEXT: [[L2_ACCUM:%.*]] = phi i32 [ [[L2_ACCUM_NEXT:%.*]], [[L2_INNER_HEADER]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[L2_IV:%.*]] = phi i64 [ [[L2_IV_NEXT:%.*]], [[L2_INNER_HEADER]] ], [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[L2_ACCUM_NEXT]] = sub i32 [[L2_ACCUM]], [[L1_EXIT_VAL]]
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; CHECK-NEXT: [[L2_DUMMY_BUT_NEED_IT:%.*]] = sext i32 [[L2_ACCUM_NEXT]] to i64
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; CHECK-NEXT: [[L2_IV_NEXT]] = add nuw nsw i64 [[L2_IV]], 1
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; CHECK-NEXT: [[L2_EXIT_COND:%.*]] = icmp ugt i64 [[L2_IV]], 11
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; CHECK-NEXT: br i1 [[L2_EXIT_COND]], label [[L2_HEADER_LOOPEXIT]], label [[L2_INNER_HEADER]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: L2.exit:
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; CHECK-NEXT: ret void
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;
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L1.preheader:
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br label %L1.header
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L1.header: ; preds = %L1.preheader, %L1.backedge
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%L1.sum = phi i32 [ %arg, %L1.preheader ], [ %L1.sum.next, %L1.backedge ]
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%L1.iv = phi i32 [ 1, %L1.preheader ], [ %L1.iv.next, %L1.backedge ]
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br i1 %c, label %L1.backedge, label %L1.early.exit
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L1.backedge: ; preds = %L1.header
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%L1.sum.next = add i32 %L1.iv, %L1.sum
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%L1.iv.next = add nuw nsw i32 %L1.iv, 1
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%L1.exit.cond = icmp ult i32 %L1.iv.next, %L1.limit
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br i1 %L1.exit.cond, label %L1.header, label %L1.exit
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L1.early.exit: ; preds = %L1.header
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ret void
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L1.exit: ; preds = %L1.backedge
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%L1.exit.val = phi i32 [ %L1.sum.next, %L1.backedge ]
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br label %L2.header
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L2.header: ; preds = %L2.Inner.header, %L1.exit, %L2.header
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switch i32 %L2.switch, label %L2.header [
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i32 8, label %L2.exit
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i32 20, label %L2.Inner.header
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]
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L2.Inner.header: ; preds = %L2.Inner.header, %L2.header
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%L2.accum = phi i32 [ %L2.accum.next, %L2.Inner.header ], [ 1, %L2.header ]
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%L2.iv = phi i64 [ %L2.iv.next, %L2.Inner.header ], [ 1, %L2.header ]
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%L2.accum.next = sub i32 %L2.accum, %L1.exit.val
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%L2.dummy.but.need.it = sext i32 %L2.accum.next to i64
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%L2.iv.next = add nuw nsw i64 %L2.iv, 1
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%L2.exit_cond = icmp ugt i64 %L2.iv, 11
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br i1 %L2.exit_cond, label %L2.header, label %L2.Inner.header
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L2.exit: ; preds = %L2.header
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ret void
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}
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