5050da7ba1
This patch adds basic assembler and MC layer infrastructure for
RISC-V big-endian targets (riscv32be/riscv64be):
- Register big-endian targets in RISCVTargetMachine
- Add big-endian data layout strings
- Implement endianness-aware fixup application in assembler
backend
- Add byte swapping for data fixups on BE cores
- Update MC layer components (AsmInfo, MCTargetDesc, Disassembler,
AsmParser)
This provides the foundation for BE support but does not yet include:
- Codegen patterns for BE
- Load/store instruction handling
- BE-specific subtarget features
870 lines
32 KiB
C++
870 lines
32 KiB
C++
//===-- RISCVDisassembler.cpp - Disassembler for RISC-V -------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVDisassembler class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "TargetInfo/RISCVTargetInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoder.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/Support/Endian.h"
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using namespace llvm;
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using namespace llvm::MCD;
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#define DEBUG_TYPE "riscv-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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namespace {
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class RISCVDisassembler : public MCDisassembler {
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std::unique_ptr<MCInstrInfo const> const MCII;
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public:
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RISCVDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
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MCInstrInfo const *MCII)
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: MCDisassembler(STI, Ctx), MCII(MCII) {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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private:
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void addSPOperands(MCInst &MI) const;
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DecodeStatus getInstruction48(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const;
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DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const;
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DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const;
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};
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} // end anonymous namespace
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static MCDisassembler *createRISCVDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new RISCVDisassembler(STI, Ctx, T.createMCInstrInfo());
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}
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extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void
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LLVMInitializeRISCVDisassembler() {
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// Register the disassembler for each target.
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64Target(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV32beTarget(),
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createRISCVDisassembler);
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TargetRegistry::RegisterMCDisassembler(getTheRISCV64beTarget(),
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createRISCVDisassembler);
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}
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static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRF16RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0_H + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRF32RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
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if (RegNo >= 32 || (IsRVE && RegNo >= 16))
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X0_W + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRX1X5RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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MCRegister Reg = RISCV::X0 + RegNo;
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if (Reg != RISCV::X1 && Reg != RISCV::X5)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR16RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_H + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR32CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_F + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR64CRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8) {
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return MCDisassembler::Fail;
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}
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MCRegister Reg = RISCV::F8_D + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeFPR128RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::F0_Q + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRNoX0RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 0)
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return MCDisassembler::Fail;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX2RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint32_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 2)
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return MCDisassembler::Fail;
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRNoX31RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo == 31) {
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return MCDisassembler::Fail;
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}
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return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::X8 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 2)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg = RI->getMatchingSuperReg(
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RISCV::X0 + RegNo, RISCV::sub_gpr_even,
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&RISCVMCRegisterClasses[RISCV::GPRPairRegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeGPRPairCRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 8 || RegNo % 2)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg = RI->getMatchingSuperReg(
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RISCV::X8 + RegNo, RISCV::sub_gpr_even,
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&RISCVMCRegisterClasses[RISCV::GPRPairCRegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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if (RegNo >= 8)
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return MCDisassembler::Fail;
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MCRegister Reg = (RegNo < 2) ? (RegNo + RISCV::X8) : (RegNo - 2 + RISCV::X18);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::V0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 2)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM2RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 4)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM4RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 32 || RegNo % 8)
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return MCDisassembler::Fail;
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const RISCVDisassembler *Dis =
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static_cast<const RISCVDisassembler *>(Decoder);
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const MCRegisterInfo *RI = Dis->getContext().getRegisterInfo();
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MCRegister Reg =
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RI->getMatchingSuperReg(RISCV::V0 + RegNo, RISCV::sub_vrm1_0,
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&RISCVMCRegisterClasses[RISCV::VRM8RegClassID]);
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeVMV0RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createReg(RISCV::V0));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeTRRegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 15)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::T0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeTRM2RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 15 || RegNo % 2)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::T0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus DecodeTRM4RegisterClass(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo > 15 || RegNo % 4)
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return MCDisassembler::Fail;
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MCRegister Reg = RISCV::T0 + RegNo;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo,
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uint64_t Address,
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const MCDisassembler *Decoder) {
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if (RegNo >= 2)
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return MCDisassembler::Fail;
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MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister;
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Inst.addOperand(MCOperand::createReg(Reg));
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return MCDisassembler::Success;
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}
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template <unsigned N>
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static DecodeStatus decodeUImmOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<N>(Imm) && "Invalid immediate");
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned Width, unsigned LowerBound>
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static DecodeStatus decodeUImmOperandGE(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<Width>(Imm) && "Invalid immediate");
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if (Imm < LowerBound)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm));
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return MCDisassembler::Success;
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}
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template <unsigned Width, unsigned LowerBound>
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static DecodeStatus decodeUImmPlus1OperandGE(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<Width>(Imm) && "Invalid immediate");
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if ((Imm + 1) < LowerBound)
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return MCDisassembler::Fail;
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Inst.addOperand(MCOperand::createImm(Imm + 1));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUImmSlistOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<3>(Imm) && "Invalid Slist immediate");
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const uint8_t Slist[] = {0, 1, 2, 4, 8, 16, 15, 31};
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Inst.addOperand(MCOperand::createImm(Slist[Imm]));
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return MCDisassembler::Success;
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}
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static DecodeStatus decodeUImmLog2XLenOperand(MCInst &Inst, uint32_t Imm,
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int64_t Address,
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const MCDisassembler *Decoder) {
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assert(isUInt<6>(Imm) && "Invalid immediate");
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if (!Decoder->getSubtargetInfo().hasFeature(RISCV::Feature64Bit) &&
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!isUInt<5>(Imm))
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return MCDisassembler::Fail;
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|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <unsigned N>
|
|
static DecodeStatus decodeUImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
if (Imm == 0)
|
|
return MCDisassembler::Fail;
|
|
return decodeUImmOperand<N>(Inst, Imm, Address, Decoder);
|
|
}
|
|
|
|
static DecodeStatus
|
|
decodeUImmLog2XLenNonZeroOperand(MCInst &Inst, uint32_t Imm, int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
if (Imm == 0)
|
|
return MCDisassembler::Fail;
|
|
return decodeUImmLog2XLenOperand(Inst, Imm, Address, Decoder);
|
|
}
|
|
|
|
template <unsigned N>
|
|
static DecodeStatus decodeUImmPlus1Operand(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<N>(Imm) && "Invalid immediate");
|
|
Inst.addOperand(MCOperand::createImm(Imm + 1));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <unsigned N>
|
|
static DecodeStatus decodeSImmOperand(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<N>(Imm) && "Invalid immediate");
|
|
// Sign-extend the number in the bottom N bits of Imm
|
|
Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
template <unsigned N>
|
|
static DecodeStatus decodeSImmNonZeroOperand(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
if (Imm == 0)
|
|
return MCDisassembler::Fail;
|
|
return decodeSImmOperand<N>(Inst, Imm, Address, Decoder);
|
|
}
|
|
|
|
template <unsigned T, unsigned N>
|
|
static DecodeStatus decodeSImmOperandAndLslN(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<T - N + 1>(Imm) && "Invalid immediate");
|
|
// Sign-extend the number in the bottom T bits of Imm after accounting for
|
|
// the fact that the T bit immediate is stored in T-N bits (the LSB is
|
|
// always zero)
|
|
Inst.addOperand(MCOperand::createImm(SignExtend64<T>(Imm << N)));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeCLUIImmOperand(MCInst &Inst, uint32_t Imm,
|
|
int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<6>(Imm) && "Invalid immediate");
|
|
if (Imm == 0)
|
|
return MCDisassembler::Fail;
|
|
Imm = SignExtend64<6>(Imm) & 0xfffff;
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeFRMArg(MCInst &Inst, uint32_t Imm, int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<3>(Imm) && "Invalid immediate");
|
|
if (!llvm::RISCVFPRndMode::isValidRoundingMode(Imm))
|
|
return MCDisassembler::Fail;
|
|
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeRTZArg(MCInst &Inst, uint32_t Imm, int64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
assert(isUInt<3>(Imm) && "Invalid immediate");
|
|
if (Imm != RISCVFPRndMode::RTZ)
|
|
return MCDisassembler::Fail;
|
|
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
bool IsRVE = Decoder->getSubtargetInfo().hasFeature(RISCV::FeatureStdExtE);
|
|
if (Imm < RISCVZC::RA || (IsRVE && Imm >= RISCVZC::RA_S0_S2))
|
|
return MCDisassembler::Fail;
|
|
Inst.addOperand(MCOperand::createImm(Imm));
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
if (Imm < RISCVZC::RA_S0)
|
|
return MCDisassembler::Fail;
|
|
return decodeZcmpRlist(Inst, Imm, Address, Decoder);
|
|
}
|
|
|
|
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder);
|
|
|
|
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder);
|
|
|
|
#include "RISCVGenDisassemblerTables.inc"
|
|
|
|
static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5);
|
|
[[maybe_unused]] DecodeStatus Result =
|
|
DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder);
|
|
assert(Result == MCDisassembler::Success && "Invalid register");
|
|
return MCDisassembler::Success;
|
|
}
|
|
|
|
static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn,
|
|
uint64_t Address,
|
|
const MCDisassembler *Decoder) {
|
|
DecodeStatus S = MCDisassembler::Success;
|
|
uint32_t Rd1 = fieldFromInstruction(Insn, 7, 5);
|
|
uint32_t Rs1 = fieldFromInstruction(Insn, 15, 5);
|
|
uint32_t Rd2 = fieldFromInstruction(Insn, 20, 5);
|
|
uint32_t UImm2 = fieldFromInstruction(Insn, 25, 2);
|
|
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
if (!Check(S, DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
if (!Check(S, DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder)))
|
|
return MCDisassembler::Fail;
|
|
[[maybe_unused]] DecodeStatus Result =
|
|
decodeUImmOperand<2>(Inst, UImm2, Address, Decoder);
|
|
assert(Result == MCDisassembler::Success && "Invalid immediate");
|
|
|
|
// Disassemble the final operand which is implicit.
|
|
unsigned Opcode = Inst.getOpcode();
|
|
bool IsWordOp = (Opcode == RISCV::TH_LWD || Opcode == RISCV::TH_LWUD ||
|
|
Opcode == RISCV::TH_SWD);
|
|
if (IsWordOp)
|
|
Inst.addOperand(MCOperand::createImm(3));
|
|
else
|
|
Inst.addOperand(MCOperand::createImm(4));
|
|
|
|
return S;
|
|
}
|
|
|
|
// Add implied SP operand for C.*SP compressed instructions. The SP operand
|
|
// isn't explicitly encoded in the instruction.
|
|
void RISCVDisassembler::addSPOperands(MCInst &MI) const {
|
|
const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
|
|
for (unsigned i = 0; i < MCID.getNumOperands(); i++)
|
|
if (MCID.operands()[i].RegClass == RISCV::SPRegClassID)
|
|
MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2));
|
|
}
|
|
|
|
namespace {
|
|
|
|
struct DecoderListEntry {
|
|
const uint8_t *Table;
|
|
FeatureBitset ContainedFeatures;
|
|
const char *Desc;
|
|
|
|
bool haveContainedFeatures(const FeatureBitset &ActiveFeatures) const {
|
|
return ContainedFeatures.none() ||
|
|
(ContainedFeatures & ActiveFeatures).any();
|
|
}
|
|
};
|
|
|
|
} // end anonymous namespace
|
|
|
|
static constexpr FeatureBitset XCVFeatureGroup = {
|
|
RISCV::FeatureVendorXCVbitmanip, RISCV::FeatureVendorXCVelw,
|
|
RISCV::FeatureVendorXCVmac, RISCV::FeatureVendorXCVmem,
|
|
RISCV::FeatureVendorXCValu, RISCV::FeatureVendorXCVsimd,
|
|
RISCV::FeatureVendorXCVbi};
|
|
|
|
static constexpr FeatureBitset XRivosFeatureGroup = {
|
|
RISCV::FeatureVendorXRivosVisni,
|
|
RISCV::FeatureVendorXRivosVizip,
|
|
};
|
|
|
|
static constexpr FeatureBitset XqciFeatureGroup = {
|
|
RISCV::FeatureVendorXqcia, RISCV::FeatureVendorXqciac,
|
|
RISCV::FeatureVendorXqcibi, RISCV::FeatureVendorXqcibm,
|
|
RISCV::FeatureVendorXqcicli, RISCV::FeatureVendorXqcicm,
|
|
RISCV::FeatureVendorXqcics, RISCV::FeatureVendorXqcicsr,
|
|
RISCV::FeatureVendorXqciint, RISCV::FeatureVendorXqciio,
|
|
RISCV::FeatureVendorXqcilb, RISCV::FeatureVendorXqcili,
|
|
RISCV::FeatureVendorXqcilia, RISCV::FeatureVendorXqcilo,
|
|
RISCV::FeatureVendorXqcilsm, RISCV::FeatureVendorXqcisim,
|
|
RISCV::FeatureVendorXqcisls, RISCV::FeatureVendorXqcisync,
|
|
};
|
|
|
|
static constexpr FeatureBitset XSfVectorGroup = {
|
|
RISCV::FeatureVendorXSfvcp, RISCV::FeatureVendorXSfvqmaccdod,
|
|
RISCV::FeatureVendorXSfvqmaccqoq, RISCV::FeatureVendorXSfvfwmaccqqq,
|
|
RISCV::FeatureVendorXSfvfnrclipxfqf, RISCV::FeatureVendorXSfmmbase};
|
|
static constexpr FeatureBitset XSfSystemGroup = {
|
|
RISCV::FeatureVendorXSiFivecdiscarddlone,
|
|
RISCV::FeatureVendorXSiFivecflushdlone,
|
|
};
|
|
|
|
static constexpr FeatureBitset XTHeadGroup = {
|
|
RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
|
|
RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
|
|
RISCV::FeatureVendorXTHeadCmo, RISCV::FeatureVendorXTHeadFMemIdx,
|
|
RISCV::FeatureVendorXTHeadMac, RISCV::FeatureVendorXTHeadMemIdx,
|
|
RISCV::FeatureVendorXTHeadMemPair, RISCV::FeatureVendorXTHeadSync,
|
|
RISCV::FeatureVendorXTHeadVdot};
|
|
|
|
static constexpr FeatureBitset XAndesGroup = {
|
|
RISCV::FeatureVendorXAndesPerf, RISCV::FeatureVendorXAndesBFHCvt,
|
|
RISCV::FeatureVendorXAndesVBFHCvt,
|
|
RISCV::FeatureVendorXAndesVSIntLoad, RISCV::FeatureVendorXAndesVPackFPH,
|
|
RISCV::FeatureVendorXAndesVDot};
|
|
|
|
static constexpr FeatureBitset XSMTGroup = {RISCV::FeatureVendorXSMTVDot};
|
|
|
|
static constexpr DecoderListEntry DecoderList32[]{
|
|
// Vendor Extensions
|
|
{DecoderTableXCV32, XCVFeatureGroup, "CORE-V extensions"},
|
|
{DecoderTableXRivos32, XRivosFeatureGroup, "Rivos"},
|
|
{DecoderTableXqci32, XqciFeatureGroup, "Qualcomm uC Extensions"},
|
|
{DecoderTableXVentana32,
|
|
{RISCV::FeatureVendorXVentanaCondOps},
|
|
"XVentanaCondOps"},
|
|
{DecoderTableXTHead32, XTHeadGroup, "T-Head extensions"},
|
|
{DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
|
|
{DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
|
|
{DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
|
|
{DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
|
|
{DecoderTableXmipscmov32,
|
|
{RISCV::FeatureVendorXMIPSCMov},
|
|
"MIPS mips.ccmov"},
|
|
{DecoderTableXmipscbop32,
|
|
{RISCV::FeatureVendorXMIPSCBOP},
|
|
"MIPS mips.pref"},
|
|
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
|
|
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
|
|
// Standard Extensions
|
|
{DecoderTable32, {}, "standard 32-bit instructions"},
|
|
{DecoderTableRV32Only32, {}, "RV32-only standard 32-bit instructions"},
|
|
{DecoderTableZfinx32, {}, "Zfinx (Float in Integer)"},
|
|
{DecoderTableZdinxRV32Only32, {}, "RV32-only Zdinx (Double in Integer)"},
|
|
};
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
if (Bytes.size() < 4) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 4;
|
|
|
|
// Use uint64_t to match getInstruction48. decodeInstruction is templated
|
|
// on the Insn type.
|
|
uint64_t Insn = support::endian::read32le(Bytes.data());
|
|
|
|
for (const DecoderListEntry &Entry : DecoderList32) {
|
|
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
|
|
DecodeStatus Result =
|
|
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
|
|
if (Result == MCDisassembler::Fail)
|
|
continue;
|
|
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static constexpr DecoderListEntry DecoderList16[]{
|
|
// Vendor Extensions
|
|
{DecoderTableXqci16, XqciFeatureGroup, "Qualcomm uC 16-bit"},
|
|
{DecoderTableXqccmp16,
|
|
{RISCV::FeatureVendorXqccmp},
|
|
"Xqccmp (Qualcomm 16-bit Push/Pop & Double Move Instructions)"},
|
|
{DecoderTableXwchc16, {RISCV::FeatureVendorXwchc}, "WCH QingKe XW"},
|
|
// Standard Extensions
|
|
// DecoderTableZicfiss16 must be checked before DecoderTable16.
|
|
{DecoderTableZicfiss16, {}, "Zicfiss (Shadow Stack 16-bit)"},
|
|
{DecoderTable16, {}, "standard 16-bit instructions"},
|
|
{DecoderTableRV32Only16, {}, "RV32-only 16-bit instructions"},
|
|
// Zc* instructions incompatible with Zcf or Zcd
|
|
{DecoderTableZcOverlap16,
|
|
{},
|
|
"ZcOverlap (16-bit Instructions overlapping with Zcf/Zcd)"},
|
|
};
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
if (Bytes.size() < 2) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 2;
|
|
|
|
// Use uint64_t to match getInstruction48. decodeInstruction is templated
|
|
// on the Insn type.
|
|
uint64_t Insn = support::endian::read16le(Bytes.data());
|
|
|
|
for (const DecoderListEntry &Entry : DecoderList16) {
|
|
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
|
|
DecodeStatus Result =
|
|
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
|
|
if (Result == MCDisassembler::Fail)
|
|
continue;
|
|
|
|
addSPOperands(MI);
|
|
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
static constexpr DecoderListEntry DecoderList48[]{
|
|
{DecoderTableXqci48, XqciFeatureGroup, "Qualcomm uC 48bit"},
|
|
};
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction48(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
if (Bytes.size() < 6) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
Size = 6;
|
|
|
|
uint64_t Insn = 0;
|
|
for (size_t i = Size; i-- != 0;)
|
|
Insn += (static_cast<uint64_t>(Bytes[i]) << 8 * i);
|
|
|
|
for (const DecoderListEntry &Entry : DecoderList48) {
|
|
if (!Entry.haveContainedFeatures(STI.getFeatureBits()))
|
|
continue;
|
|
|
|
LLVM_DEBUG(dbgs() << "Trying " << Entry.Desc << " table:\n");
|
|
DecodeStatus Result =
|
|
decodeInstruction(Entry.Table, MI, Insn, Address, this, STI);
|
|
if (Result == MCDisassembler::Fail)
|
|
continue;
|
|
|
|
return Result;
|
|
}
|
|
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
|
|
ArrayRef<uint8_t> Bytes,
|
|
uint64_t Address,
|
|
raw_ostream &CS) const {
|
|
CommentStream = &CS;
|
|
// It's a 16 bit instruction if bit 0 and 1 are not 0b11.
|
|
if ((Bytes[0] & 0b11) != 0b11)
|
|
return getInstruction16(MI, Size, Bytes, Address, CS);
|
|
|
|
// It's a 32 bit instruction if bit 1:0 are 0b11(checked above) and bits 4:2
|
|
// are not 0b111.
|
|
if ((Bytes[0] & 0b1'1100) != 0b1'1100)
|
|
return getInstruction32(MI, Size, Bytes, Address, CS);
|
|
|
|
// 48-bit instructions are encoded as 0bxx011111.
|
|
if ((Bytes[0] & 0b11'1111) == 0b01'1111) {
|
|
return getInstruction48(MI, Size, Bytes, Address, CS);
|
|
}
|
|
|
|
// 64-bit instructions are encoded as 0x0111111.
|
|
if ((Bytes[0] & 0b111'1111) == 0b011'1111) {
|
|
Size = Bytes.size() >= 8 ? 8 : 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
// Remaining cases need to check a second byte.
|
|
if (Bytes.size() < 2) {
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
// 80-bit through 176-bit instructions are encoded as 0bxnnnxxxx_x1111111.
|
|
// Where the number of bits is (80 + (nnn * 16)) for nnn != 0b111.
|
|
unsigned nnn = (Bytes[1] >> 4) & 0b111;
|
|
if (nnn != 0b111) {
|
|
Size = 10 + (nnn * 2);
|
|
if (Bytes.size() < Size)
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|
|
|
|
// Remaining encodings are reserved for > 176-bit instructions.
|
|
Size = 0;
|
|
return MCDisassembler::Fail;
|
|
}
|