5050da7ba1
This patch adds basic assembler and MC layer infrastructure for
RISC-V big-endian targets (riscv32be/riscv64be):
- Register big-endian targets in RISCVTargetMachine
- Add big-endian data layout strings
- Implement endianness-aware fixup application in assembler
backend
- Add byte swapping for data fixups on BE cores
- Update MC layer components (AsmInfo, MCTargetDesc, Disassembler,
AsmParser)
This provides the foundation for BE support but does not yet include:
- Codegen patterns for BE
- Load/store instruction handling
- BE-specific subtarget features
24 lines
733 B
C++
24 lines
733 B
C++
//===-- RISCVTargetInfo.h - RISC-V Target Implementation --------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H
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#define LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H
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namespace llvm {
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class Target;
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Target &getTheRISCV32Target();
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Target &getTheRISCV64Target();
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Target &getTheRISCV32beTarget();
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Target &getTheRISCV64beTarget();
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} // namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_TARGETINFO_RISCVTARGETINFO_H
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