
This patch adds basic assembler and MC layer infrastructure for RISC-V big-endian targets (riscv32be/riscv64be): - Register big-endian targets in RISCVTargetMachine - Add big-endian data layout strings - Implement endianness-aware fixup application in assembler backend - Add byte swapping for data fixups on BE cores - Update MC layer components (AsmInfo, MCTargetDesc, Disassembler, AsmParser) This provides the foundation for BE support but does not yet include: - Codegen patterns for BE - Load/store instruction handling - BE-specific subtarget features
37 lines
1.2 KiB
ArmAsm
37 lines
1.2 KiB
ArmAsm
# RUN: llvm-mc -filetype=obj -triple=riscv32be %s -o %t.32be.o
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# RUN: llvm-objdump -s %t.32be.o | FileCheck -check-prefix=RV32BE %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64be %s -o %t.64be.o
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# RUN: llvm-objdump -s %t.64be.o | FileCheck -check-prefix=RV64BE %s
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# RUN: llvm-mc -filetype=obj -triple=riscv32 %s -o %t.32le.o
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# RUN: llvm-objdump -s %t.32le.o | FileCheck -check-prefix=RV32LE %s
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# RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t.64le.o
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# RUN: llvm-objdump -s %t.64le.o | FileCheck -check-prefix=RV64LE %s
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# Test that data directives are properly byte-swapped on big-endian RISC-V
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.data
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byte_data:
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.byte 0x11
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.byte 0x22
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.half 0x3344
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.word 0x55667788
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.long 0x99aabbcc
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.quad 0x1122334455667788
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# RV32BE: Contents of section .data:
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# RV32BE-NEXT: 0000 11223344 55667788 99aabbcc 11223344
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# RV32BE-NEXT: 0010 55667788
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# RV64BE: Contents of section .data:
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# RV64BE-NEXT: 0000 11223344 55667788 99aabbcc 11223344
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# RV64BE-NEXT: 0010 55667788
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# RV32LE: Contents of section .data:
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# RV32LE-NEXT: 0000 11224433 88776655 ccbbaa99 88776655
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# RV32LE-NEXT: 0010 44332211
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# RV64LE: Contents of section .data:
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# RV64LE-NEXT: 0000 11224433 88776655 ccbbaa99 88776655
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# RV64LE-NEXT: 0010 44332211
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