5050da7ba1
This patch adds basic assembler and MC layer infrastructure for
RISC-V big-endian targets (riscv32be/riscv64be):
- Register big-endian targets in RISCVTargetMachine
- Add big-endian data layout strings
- Implement endianness-aware fixup application in assembler
backend
- Add byte swapping for data fixups on BE cores
- Update MC layer components (AsmInfo, MCTargetDesc, Disassembler,
AsmParser)
This provides the foundation for BE support but does not yet include:
- Codegen patterns for BE
- Load/store instruction handling
- BE-specific subtarget features
47 lines
1.3 KiB
ArmAsm
47 lines
1.3 KiB
ArmAsm
# RUN: llvm-mc %s -filetype=obj -triple=riscv32be | llvm-readobj -h - \
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# RUN: | FileCheck -check-prefix=RV32BE %s
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# RUN: llvm-mc %s -filetype=obj -triple=riscv64be | llvm-readobj -h - \
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# RUN: | FileCheck -check-prefix=RV64BE %s
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# Test that RISC-V big-endian targets produce correct ELF headers
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# RV32BE: Format: elf32-bigriscv
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# RV32BE: Arch: riscv32
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# RV32BE: AddressSize: 32bit
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# RV32BE: ElfHeader {
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# RV32BE: Ident {
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# RV32BE: Magic: (7F 45 4C 46)
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# RV32BE: Class: 32-bit (0x1)
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# RV32BE: DataEncoding: BigEndian (0x2)
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# RV32BE: FileVersion: 1
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# RV32BE: OS/ABI: SystemV (0x0)
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# RV32BE: ABIVersion: 0
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# RV32BE: }
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# RV32BE: Type: Relocatable (0x1)
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# RV32BE: Machine: EM_RISCV (0xF3)
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# RV32BE: Version: 1
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# RV32BE: Flags [ (0x0)
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# RV32BE: ]
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# RV32BE: }
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# RV64BE: Format: elf64-bigriscv
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# RV64BE: Arch: riscv64
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# RV64BE: AddressSize: 64bit
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# RV64BE: ElfHeader {
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# RV64BE: Ident {
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# RV64BE: Magic: (7F 45 4C 46)
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# RV64BE: Class: 64-bit (0x2)
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# RV64BE: DataEncoding: BigEndian (0x2)
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# RV64BE: FileVersion: 1
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# RV64BE: OS/ABI: SystemV (0x0)
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# RV64BE: ABIVersion: 0
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# RV64BE: }
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# RV64BE: Type: Relocatable (0x1)
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# RV64BE: Machine: EM_RISCV (0xF3)
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# RV64BE: Version: 1
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# RV64BE: Flags [ (0x0)
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# RV64BE: ]
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# RV64BE: }
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nop
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