eefed1dbf0
This is a replacement for the original fix attempted in c46aab01c002b7a04135b8b7f1f52d8c9ae23a58. This fixes "overlapping insert" assertion failures when trying to unwind an unsuccessful recoloring attempt. The problem would occur when there are multiple recoloring candidates which recursively required recoloring. If one recoloring candidate was successfully recolored at one level, and the next recoloring candidate was unsuccessful, we would not roll back the first candidates successful recoloring. The forgotten successful recoloring may have been assigned to something that conflicts with a register that needs to be restored in a parent recoloring attempt. See the testcase added in issue48473 for a more concrete example with explanation.
62 lines
3.1 KiB
YAML
62 lines
3.1 KiB
YAML
# RUN: not llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs=0 -start-before=greedy,1 -stop-after=virtregrewriter,1 %s -o /dev/null 2>&1 | FileCheck -check-prefix=ERR %s
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# RUN: not --crash llc -march=amdgcn -mcpu=gfx908 -verify-machineinstrs -start-before=greedy,1 -stop-after=virtregrewriter,1 %s -o /dev/null 2>&1 | FileCheck -check-prefixes=ERR,VERIFIER %s
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# FIXME: We should not produce a verifier error after erroring
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# ERR: error: inline assembly requires more registers than available
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# VERIFIER: *** Bad machine code: Using an undefined physical register ***
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# This testcase cannot be compiled with the enforced register
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# budget. Previously, tryLastChanceRecoloring would assert here. It
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# was attempting to recolor a superregister with an overlapping
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# subregister over the same range.
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--- |
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define void @foo() #0 {
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ret void
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}
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attributes #0 = { "amdgpu-waves-per-eu"="8,8" }
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...
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---
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name: foo
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tracksRegLiveness: true
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registers:
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- { id: 0, class: vgpr_32 }
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- { id: 1, class: vgpr_32 }
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- { id: 2, class: vreg_512 }
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- { id: 3, class: vreg_256 }
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- { id: 4, class: vreg_128 }
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- { id: 5, class: vreg_96 }
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- { id: 6, class: vreg_96 }
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- { id: 7, class: vreg_512 }
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- { id: 8, class: vreg_256 }
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- { id: 9, class: vreg_128 }
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- { id: 10, class: vreg_96 }
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- { id: 11, class: vreg_96 }
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- { id: 12, class: sreg_64 }
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- { id: 13, class: sgpr_64 }
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- { id: 14, class: vgpr_32 }
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machineFunctionInfo:
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scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'
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frameOffsetReg: '$sgpr33'
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stackPtrOffsetReg: '$sgpr32'
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body: |
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bb.0:
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INLINEASM &"; def $0", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $agpr0
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%14:vgpr_32 = COPY killed $agpr0
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INLINEASM &"; def $0 $1 $2 $3 $4", 1 /* sideeffect attdialect */, 11534346 /* regdef:VReg_512 */, def %7, 10158090 /* regdef:VReg_256 */, def %8, 4784138 /* regdef:VReg_128 */, def %9, 3670026 /* regdef:VReg_96 */, def %10, 3670026 /* regdef:VReg_96 */, def %11
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INLINEASM &"; clobber", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $agpr0_agpr1_agpr2_agpr3_agpr4_agpr5_agpr6_agpr7_agpr8_agpr9_agpr10_agpr11_agpr12_agpr13_agpr14_agpr15_agpr16_agpr17_agpr18_agpr19_agpr20_agpr21_agpr22_agpr23_agpr24_agpr25_agpr26_agpr27_agpr28_agpr29_agpr30_agpr31, 12 /* clobber */, implicit-def dead early-clobber $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15_vgpr16_vgpr17_vgpr18_vgpr19_vgpr20_vgpr21_vgpr22_vgpr23_vgpr24_vgpr25_vgpr26_vgpr27_vgpr28_vgpr29_vgpr30_vgpr31
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 11534345 /* reguse:VReg_512 */, %7
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 10158089 /* reguse:VReg_256 */, %8
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 4784137 /* reguse:VReg_128 */, %9
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %10
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 3670025 /* reguse:VReg_96 */, %11
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$agpr1 = COPY %14
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INLINEASM &"; use $0", 1 /* sideeffect attdialect */, 9 /* reguse */, killed $agpr1
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SI_RETURN
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...
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