llvm-project/llvm/test/MC/RISCV/fixups-binary-expression.s
Fangrui Song 53edb1a160 [test] Improve linker-relaxable fixups tests
The behavior will change once the assembler improves (#140692)
2025-05-21 22:08:55 -07:00

36 lines
836 B
ArmAsm

# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c < %s \
# RUN: | llvm-objdump -M no-aliases -dr - \
# RUN: | FileCheck -check-prefix=CHECK-INSTR %s
# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+c,+relax < %s \
# RUN: | llvm-readobj -r - | FileCheck -check-prefix=CHECK-RELOC %s
.LBB0:
.LBB1:
## This is linker-relaxable to avoid resolving the following fixups
call relax
jal zero, .LBB0+16
# CHECK-INSTR: jal zero, 0x10
# CHECK-RELOC: R_RISCV_JAL
beq a0, a1, .LBB1+32
# CHECK-INSTR: beq a0, a1, 0x20
# CHECK-RELOC-NEXT: R_RISCV_BRANCH
c.j .+32
# CHECK-INSTR: c.j 0x30
# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
c.j .LBB2+4
# CHECK-INSTR: c.j 0x22
# CHECK-RELOC-NEXT: R_RISCV_RVC_JUMP
c.beqz a0, .-2
# CHECK-INSTR: c.beqz a0, 0x12
# CHECK-RELOC-NEXT: R_RISCV_RVC_BRANCH
call relax
.LBB2: