a1bdf8f545
Many OpenMP Clang tests do not RUN for version 4.5 and the default version. This second patch in the series handles test cases which require updation in CHECK lines along with adding RUN lines for the default version. It involves updating line number of pragmas. Reviewed By: ABataev Differential Revision: https://reviews.llvm.org/D85150
115 lines
6.5 KiB
C++
115 lines
6.5 KiB
C++
// Test target codegen - host bc file has to be created first.
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm-bc %s -o %t-ppc-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple i386-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm-bc %s -o %t-x86-host.bc
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// RUN: %clang_cc1 -verify -fopenmp -fopenmp-cuda-mode -fexceptions -fcxx-exceptions -x c++ -triple nvptx-unknown-unknown -fopenmp-targets=nvptx-nvidia-cuda -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - -disable-llvm-optzns | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
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// expected-no-diagnostics
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#ifndef HEADER
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#define HEADER
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// Check that the execution mode of all 2 target regions on the gpu is set to non-SPMD Mode.
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// CHECK-DAG: {{@__omp_offloading_.+l28}}_exec_mode = weak constant i8 0
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// CHECK-DAG: {{@__omp_offloading_.+l33}}_exec_mode = weak constant i8 0
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template<typename tx>
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tx ftemplate(int n) {
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tx a = 0;
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short aa = 0;
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tx b[10];
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#pragma omp target parallel map(tofrom: aa) num_threads(1024)
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{
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aa += 1;
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}
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#pragma omp target parallel map(tofrom:a, aa, b) if(target: n>40) num_threads(n)
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{
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a += 1;
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aa += 1;
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b[2] += 1;
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}
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return a;
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}
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int bar(int n){
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int a = 0;
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a += ftemplate<int>(n);
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return a;
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}
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l28}}(
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1, i16 0)
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// CHECK: call void @__kmpc_data_sharing_init_stack_spmd()
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// CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{.+}})
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// CHECK: store i32 [[GTID]], i32* [[THREADID:%.+]],
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// CHECK: call void [[OUTLINED:@.+]](i32* [[THREADID]], i32* %{{.+}}, i16* [[AA]])
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// CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
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// CHECK: ret void
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// CHECK: }
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// CHECK: define internal void [[OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i16* {{[^%]*}}[[ARG:%.+]])
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// CHECK: = alloca i32*, align
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// CHECK: = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: store i16* [[ARG]], i16** [[AA_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[VAL:%.+]] = load i16, i16* [[AA]], align
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// CHECK: store i16 {{%.+}}, i16* [[AA]], align
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// CHECK: ret void
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// CHECK: }
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// CHECK-LABEL: define {{.*}}void {{@__omp_offloading_.+template.+l33}}(
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// CHECK: [[A_ADDR:%.+]] = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
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// CHECK: store i32* {{%.+}}, i32** [[A_ADDR]], align
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// CHECK: store i16* {{%.+}}, i16** [[AA_ADDR]], align
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// CHECK: store [10 x i32]* {{%.+}}, [10 x i32]** [[B_ADDR]], align
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// CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
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// CHECK: [[THREAD_LIMIT:%.+]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x()
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// CHECK: call void @__kmpc_spmd_kernel_init(i32 [[THREAD_LIMIT]], i16 1, i16 0)
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// CHECK: call void @__kmpc_data_sharing_init_stack_spmd()
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// CHECK: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @{{.+}})
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// CHECK: store i32 [[GTID]], i32* [[THREADID:%.+]],
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// CHECK: call void [[OUTLINED:@.+]](i32* [[THREADID]], i32* %{{.+}}, i32* [[A]], i16* [[AA]], [10 x i32]* [[B]])
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// CHECK: call void @__kmpc_spmd_kernel_deinit_v2(i16 1)
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// CHECK: ret void
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// CHECK: }
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// CHECK: define internal void [[OUTLINED]](i32* noalias %{{.+}}, i32* noalias %{{.+}}, i32* {{[^%]*}}[[ARG1:%.+]], i16* {{[^%]*}}[[ARG2:%.+]], [10 x i32]* {{[^%]*}}[[ARG3:%.+]])
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// CHECK: = alloca i32*, align
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// CHECK: = alloca i32*, align
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// CHECK: [[A_ADDR:%.+]] = alloca i32*, align
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// CHECK: [[AA_ADDR:%.+]] = alloca i16*, align
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// CHECK: [[B_ADDR:%.+]] = alloca [10 x i32]*, align
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// CHECK: store i32* [[ARG1]], i32** [[A_ADDR]], align
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// CHECK: store i16* [[ARG2]], i16** [[AA_ADDR]], align
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// CHECK: store [10 x i32]* [[ARG3]], [10 x i32]** [[B_ADDR]], align
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// CHECK: [[A:%.+]] = load i32*, i32** [[A_ADDR]], align
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// CHECK: [[AA:%.+]] = load i16*, i16** [[AA_ADDR]], align
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// CHECK: [[B:%.+]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align
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// CHECK: store i32 {{%.+}}, i32* [[A]], align
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// CHECK: store i16 {{%.+}}, i16* [[AA]], align
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// CHECK: [[ELT:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]],
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// CHECK: store i32 {{%.+}}, i32* [[ELT]], align
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// CHECK: ret void
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// CHECK: }
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#endif
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