f7a7efbf88
Even though wide vectors are legal they still cost more as we will have to eventually split them. Not all operations can be uniformly done on vector types. Conservatively add the cost of splitting at least to 8 dwords, which is our widest possible load. We are more or less lying to cost mode with this change but this can prevent vectorizer from creation of wide vectors which results in RA problems for us. Differential Revision: https://reviews.llvm.org/D83078
131 lines
5.1 KiB
LLVM
131 lines
5.1 KiB
LLVM
; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SLOW16,ALL %s
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; RUN: opt -cost-model -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=FAST16,ALL %s
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; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa < %s | FileCheck -check-prefixes=SLOW16,ALL %s
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; RUN: opt -cost-model -cost-kind=code-size -analyze -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=FAST16,ALL %s
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; ALL: 'mul_i32'
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; ALL: estimated cost of 3 for {{.*}} mul i32
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define amdgpu_kernel void @mul_i32(i32 addrspace(1)* %out, i32 addrspace(1)* %vaddr, i32 %b) #0 {
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%vec = load i32, i32 addrspace(1)* %vaddr
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%mul = mul i32 %vec, %b
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store i32 %mul, i32 addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v2i32'
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; ALL: estimated cost of 6 for {{.*}} mul <2 x i32>
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define amdgpu_kernel void @mul_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %vaddr, <2 x i32> %b) #0 {
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%vec = load <2 x i32>, <2 x i32> addrspace(1)* %vaddr
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%mul = mul <2 x i32> %vec, %b
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store <2 x i32> %mul, <2 x i32> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v3i32'
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; Allow for 12 when v3i32 is illegal and TargetLowering thinks it needs widening,
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; and 9 when it is legal.
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; ALL: estimated cost of {{9|12}} for {{.*}} mul <3 x i32>
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define amdgpu_kernel void @mul_v3i32(<3 x i32> addrspace(1)* %out, <3 x i32> addrspace(1)* %vaddr, <3 x i32> %b) #0 {
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%vec = load <3 x i32>, <3 x i32> addrspace(1)* %vaddr
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%mul = mul <3 x i32> %vec, %b
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store <3 x i32> %mul, <3 x i32> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v5i32'
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; Allow for 24 when v5i32 is illegal and TargetLowering thinks it needs widening,
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; and 15 when it is legal.
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; ALL: estimated cost of {{15|24}} for {{.*}} mul <5 x i32>
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define amdgpu_kernel void @mul_v5i32(<5 x i32> addrspace(1)* %out, <5 x i32> addrspace(1)* %vaddr, <5 x i32> %b) #0 {
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%vec = load <5 x i32>, <5 x i32> addrspace(1)* %vaddr
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%mul = mul <5 x i32> %vec, %b
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store <5 x i32> %mul, <5 x i32> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v4i32'
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; ALL: estimated cost of 12 for {{.*}} mul <4 x i32>
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define amdgpu_kernel void @mul_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %vaddr, <4 x i32> %b) #0 {
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%vec = load <4 x i32>, <4 x i32> addrspace(1)* %vaddr
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%mul = mul <4 x i32> %vec, %b
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store <4 x i32> %mul, <4 x i32> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_i64'
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; ALL: estimated cost of 16 for {{.*}} mul i64
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define amdgpu_kernel void @mul_i64(i64 addrspace(1)* %out, i64 addrspace(1)* %vaddr, i64 %b) #0 {
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%vec = load i64, i64 addrspace(1)* %vaddr
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%mul = mul i64 %vec, %b
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store i64 %mul, i64 addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v2i64'
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; ALL: estimated cost of 32 for {{.*}} mul <2 x i64>
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define amdgpu_kernel void @mul_v2i64(<2 x i64> addrspace(1)* %out, <2 x i64> addrspace(1)* %vaddr, <2 x i64> %b) #0 {
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%vec = load <2 x i64>, <2 x i64> addrspace(1)* %vaddr
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%mul = mul <2 x i64> %vec, %b
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store <2 x i64> %mul, <2 x i64> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v3i64'
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; ALL: estimated cost of 48 for {{.*}} mul <3 x i64>
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define amdgpu_kernel void @mul_v3i64(<3 x i64> addrspace(1)* %out, <3 x i64> addrspace(1)* %vaddr, <3 x i64> %b) #0 {
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%vec = load <3 x i64>, <3 x i64> addrspace(1)* %vaddr
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%mul = mul <3 x i64> %vec, %b
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store <3 x i64> %mul, <3 x i64> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v4i64'
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; ALL: estimated cost of 64 for {{.*}} mul <4 x i64>
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define amdgpu_kernel void @mul_v4i64(<4 x i64> addrspace(1)* %out, <4 x i64> addrspace(1)* %vaddr, <4 x i64> %b) #0 {
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%vec = load <4 x i64>, <4 x i64> addrspace(1)* %vaddr
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%mul = mul <4 x i64> %vec, %b
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store <4 x i64> %mul, <4 x i64> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v8i64'
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; ALL: estimated cost of 256 for {{.*}} mul <8 x i64>
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define amdgpu_kernel void @mul_v8i64(<8 x i64> addrspace(1)* %out, <8 x i64> addrspace(1)* %vaddr, <8 x i64> %b) #0 {
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%vec = load <8 x i64>, <8 x i64> addrspace(1)* %vaddr
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%mul = mul <8 x i64> %vec, %b
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store <8 x i64> %mul, <8 x i64> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_i16'
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; ALL: estimated cost of 3 for {{.*}} mul i16
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define amdgpu_kernel void @mul_i16(i16 addrspace(1)* %out, i16 addrspace(1)* %vaddr, i16 %b) #0 {
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%vec = load i16, i16 addrspace(1)* %vaddr
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%mul = mul i16 %vec, %b
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store i16 %mul, i16 addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v2i16'
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; SLOW16: estimated cost of 6 for {{.*}} mul <2 x i16>
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; FAST16: estimated cost of 3 for {{.*}} mul <2 x i16>
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define amdgpu_kernel void @mul_v2i16(<2 x i16> addrspace(1)* %out, <2 x i16> addrspace(1)* %vaddr, <2 x i16> %b) #0 {
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%vec = load <2 x i16>, <2 x i16> addrspace(1)* %vaddr
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%mul = mul <2 x i16> %vec, %b
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store <2 x i16> %mul, <2 x i16> addrspace(1)* %out
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ret void
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}
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; ALL: 'mul_v3i16'
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; SLOW16: estimated cost of 12 for {{.*}} mul <3 x i16>
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; FAST16: estimated cost of 6 for {{.*}} mul <3 x i16>
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define amdgpu_kernel void @mul_v3i16(<3 x i16> addrspace(1)* %out, <3 x i16> addrspace(1)* %vaddr, <3 x i16> %b) #0 {
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%vec = load <3 x i16>, <3 x i16> addrspace(1)* %vaddr
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%mul = mul <3 x i16> %vec, %b
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store <3 x i16> %mul, <3 x i16> addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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