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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-pattern-add3.mir
Matt Arsenault 79f67cae91 AMDGPU: Rename add/sub with carry out instructions 
The hardware has created a real mess in the naming for add/sub, which
have been renamed basically every generation. Switch the carry out
pseudos to have the gfx9/gfx10 names. We were using the original SI/CI
v_add_i32/v_sub_i32 names. Later targets reintroduced these names as
carryless instructions with a saturating clamp bit, which we do not
define. Do this rename so we can unambiguously add these missing
instructions.

The carry-in versions should also be renamed, but at least those had a
consistent _u32 name to begin with. The 16-bit instructions were also
renamed, but aren't ambiguous.

This does regress assembler error message quality in some cases. In
mismatched wave32/wave64 situations, this will switch from
"unsupported instruction" to "invalid operand", with the error
pointing at the wrong position. I couldn't quite follow how the
assembler selects these, but the previous behavior seemed accidental
to me. It looked like there was a partial attempt to handle this which
was never completed (i.e. there is an AMDGPUOperand::isBoolReg but it
isn't used for anything).
2020-07-16 13:16:30 -04:00

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX8 %s
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX9 %s
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck -check-prefix=GFX10 %s
---
name: add_s32_sgpr_sgpr_sgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $sgpr0, $sgpr1, $sgpr2
; GFX8-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX8: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX8: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX8: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX8: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX8: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX8: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX8: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
; GFX9-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX9: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX9: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX9: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX9: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX9: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX9: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX9: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
; GFX10-LABEL: name: add_s32_sgpr_sgpr_sgpr
; GFX10: liveins: $sgpr0, $sgpr1, $sgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX10: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
; GFX10: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX10: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY]], [[COPY1]], implicit-def $scc
; GFX10: [[S_ADD_I32_1:%[0-9]+]]:sreg_32 = S_ADD_I32 [[S_ADD_I32_]], [[COPY2]], implicit-def $scc
; GFX10: S_ENDPGM 0, implicit [[S_ADD_I32_1]]
%0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s32) = COPY $sgpr1
%2:sgpr(s32) = COPY $sgpr2
%3:sgpr(s32) = G_ADD %0, %1
%4:sgpr(s32) = G_ADD %3, %2
S_ENDPGM 0, implicit %4
...
---
name: add_s32_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_s32_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_s32_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD3_U32_:%[0-9]+]]:vgpr_32 = V_ADD3_U32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD3_U32_]]
; GFX10-LABEL: name: add_s32_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD3_U32_:%[0-9]+]]:vgpr_32 = V_ADD3_U32 [[COPY]], [[COPY1]], [[COPY2]], implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD3_U32_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_ADD %0, %1
%4:vgpr(s32) = G_ADD %3, %2
S_ENDPGM 0, implicit %4
...
---
name: add_s32_vgpr_vgpr_vgpr_multi_use
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_s32_vgpr_vgpr_vgpr_multi_use
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4, implicit %3
; GFX9-LABEL: name: add_s32_vgpr_vgpr_vgpr_multi_use
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_]]
; GFX10-LABEL: name: add_s32_vgpr_vgpr_vgpr_multi_use
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]], implicit [[V_ADD_U32_e64_]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(s32) = G_ADD %0, %1
%4:vgpr(s32) = G_ADD %3, %2
S_ENDPGM 0, implicit %4, implicit %3
...
---
name: add_p3_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p3_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(p3) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(p3) = G_PTR_ADD %0, %1
%4:vgpr(p3) = G_PTR_ADD %3, %2
S_ENDPGM 0, implicit %4
...
---
name: add_p5_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 %3, [[COPY2]], 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p5_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], [[COPY2]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(p5) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(s32) = COPY $vgpr2
%3:vgpr(p5) = G_PTR_ADD %0, %1
%4:vgpr(p5) = G_PTR_ADD %3, %2
S_ENDPGM 0, implicit %4
...
---
name: add_p3_s32_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p3_s32_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], %3, 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p3_s32_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p3_s32_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(p3) = COPY $vgpr2
%3:vgpr(s32) = G_ADD %0, %1
%4:vgpr(p3) = G_PTR_ADD %2, %3
S_ENDPGM 0, implicit %4
...
---
name: add_p5_s32_vgpr_vgpr_vgpr
legalized: true
regBankSelected: true
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8-LABEL: name: add_p5_s32_vgpr_vgpr_vgpr
; GFX8: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX8: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX8: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX8: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX8: %3:vgpr_32, dead %6:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX8: %4:vgpr_32, dead %5:sreg_64_xexec = V_ADD_CO_U32_e64 [[COPY2]], %3, 0, implicit $exec
; GFX8: S_ENDPGM 0, implicit %4
; GFX9-LABEL: name: add_p5_s32_vgpr_vgpr_vgpr
; GFX9: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX9: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX9: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX9: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX9: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX9: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX9: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
; GFX10-LABEL: name: add_p5_s32_vgpr_vgpr_vgpr
; GFX10: liveins: $vgpr0, $vgpr1, $vgpr2
; GFX10: $vcc_hi = IMPLICIT_DEF
; GFX10: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX10: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX10: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX10: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY]], [[COPY1]], 0, implicit $exec
; GFX10: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY2]], [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX10: S_ENDPGM 0, implicit [[V_ADD_U32_e64_1]]
%0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = COPY $vgpr1
%2:vgpr(p5) = COPY $vgpr2
%3:vgpr(s32) = G_ADD %0, %1
%4:vgpr(p5) = G_PTR_ADD %2, %3
S_ENDPGM 0, implicit %4
...
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