4b4496312e
This is the groundwork required to implement strictfp. For now, this should be NFC for regular instructoins (many instructions just gain an extra use of a reserved register). Regalloc won't rematerialize instructions with reads of physical registers, but we were suffering from that anyway with the exec reads. Should add it for all the related FP uses (possibly with some extras). I did not add it to either the gpr index mode instructions (or every single VALU instruction) since it's a ridiculous feature already modeled as an arbitrary side effect. Also work towards marking instructions with FP exceptions. This doesn't actually set the bit yet since this would start to change codegen. It seems nofpexcept is currently not implied from the regular IR FP operations. Add it to some MIR tests where I think it might matter.
200 lines
5.7 KiB
YAML
200 lines
5.7 KiB
YAML
# RUN: llc -march=amdgcn -mcpu=gfx803 -run-pass simple-register-coalescing -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s
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#
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# This test gave "Use not jointly dominated by defs" when
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# removePartialRedundancy attempted to prune and then re-extend a subrange.
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#
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# GCN: {{^body}}
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---
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name: _amdgpu_ps_main
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tracksRegLiveness: true
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body: |
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bb.0:
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successors: %bb.1, %bb.2
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%21:vgpr_32 = nofpexcept V_TRUNC_F32_e32 undef %22:vgpr_32, implicit $mode, implicit $exec
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%23:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 killed %21, implicit $mode, implicit $exec
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%108:vgpr_32 = V_LSHRREV_B32_e32 4, killed %23, implicit $exec
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undef %109.sub1:vreg_128 = COPY %108
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%28:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %29:sgpr_128, 3044, 0, 0 :: (dereferenceable invariant load 4)
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S_CMP_EQ_U32 killed %28, 0, implicit-def $scc
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S_CBRANCH_SCC0 %bb.2, implicit killed $scc
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bb.1:
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%138:vreg_128 = COPY killed %109
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S_BRANCH %bb.9
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bb.2:
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successors: %bb.3, %bb.4
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S_CBRANCH_SCC0 %bb.4, implicit undef $scc
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bb.3:
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%136:vreg_128 = COPY killed %109
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S_BRANCH %bb.5
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bb.4:
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%136:vreg_128 = COPY killed %109
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bb.5:
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successors: %bb.6, %bb.8
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%110:vreg_128 = COPY killed %136
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dead %32:sreg_32_xm0 = S_MOV_B32 0
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%111:vreg_128 = COPY %110
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%111.sub3:vreg_128 = COPY undef %32
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S_CBRANCH_SCC1 %bb.8, implicit undef $scc
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S_BRANCH %bb.6
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bb.6:
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%36:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %37:sgpr_128, 2708, 0, 0 :: (dereferenceable invariant load 4)
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%39:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %110.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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%40:vgpr_32 = nofpexcept V_MAD_F32 0, %111.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 0, 0, 0, implicit $mode, implicit $exec
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%41:vgpr_32 = nofpexcept V_MUL_F32_e64 0, 0, 0, killed %40, 1, 0, implicit $mode, implicit $exec
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%43:vgpr_32 = nofpexcept V_MUL_F32_e32 0, %39, implicit $mode, implicit $exec
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%44:vgpr_32 = COPY killed %43
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%44:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %41, %44, implicit $mode, implicit $exec
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%47:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
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%46:vgpr_32 = COPY killed %47
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%46:vgpr_32 = nofpexcept V_MAC_F32_e32 0, killed %39, %46, implicit $mode, implicit $exec
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undef %115.sub0:vreg_128 = COPY %46
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%115.sub1:vreg_128 = COPY killed %46
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%115.sub2:vreg_128 = COPY killed %44
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%50:sreg_64_xexec = V_CMP_NE_U32_e64 0, killed %36, implicit $exec
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dead %118:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%137:vreg_128 = IMPLICIT_DEF
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bb.7:
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successors: %bb.7, %bb.8
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%119:vreg_128 = COPY killed %137
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%121:vreg_128 = COPY killed %119
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%121.sub3:vreg_128 = COPY undef %32
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%56:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub2, %121.sub2, implicit $mode, implicit $exec
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%59:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub1, %121.sub1, implicit $mode, implicit $exec
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%62:vgpr_32 = nofpexcept V_ADD_F32_e32 %115.sub0, killed %121.sub0, implicit $mode, implicit $exec
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undef %117.sub0:vreg_128 = COPY killed %62
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%117.sub1:vreg_128 = COPY killed %59
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%117.sub2:vreg_128 = COPY killed %56
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%64:sreg_64 = S_AND_B64 $exec, %50, implicit-def dead $scc
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$vcc = COPY killed %64
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%137:vreg_128 = COPY killed %117
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S_CBRANCH_VCCNZ %bb.7, implicit killed $vcc
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S_BRANCH %bb.8
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bb.8:
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dead %66:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM undef %67:sgpr_128, 2704, 0, 0 :: (dereferenceable invariant load 4)
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%138:vreg_128 = COPY killed %111
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bb.9:
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%113:vreg_128 = COPY killed %138
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S_CBRANCH_SCC1 %bb.18, implicit undef $scc
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S_BRANCH %bb.10
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bb.10:
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S_CBRANCH_SCC1 %bb.12, implicit undef $scc
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S_BRANCH %bb.11
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bb.11:
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bb.12:
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successors: %bb.13, %bb.18
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S_CBRANCH_SCC1 %bb.18, implicit undef $scc
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S_BRANCH %bb.13
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bb.13:
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successors: %bb.14, %bb.17
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S_CBRANCH_SCC1 %bb.17, implicit undef $scc
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S_BRANCH %bb.14
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bb.14:
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S_CBRANCH_SCC1 %bb.16, implicit undef $scc
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S_BRANCH %bb.15
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bb.15:
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bb.16:
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bb.17:
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bb.18:
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S_CBRANCH_SCC1 %bb.26, implicit undef $scc
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S_BRANCH %bb.19
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bb.19:
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S_CBRANCH_SCC1 %bb.26, implicit undef $scc
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S_BRANCH %bb.20
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bb.20:
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S_CBRANCH_SCC1 %bb.25, implicit undef $scc
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S_BRANCH %bb.21
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bb.21:
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successors: %bb.22, %bb.24
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S_CBRANCH_SCC1 %bb.24, implicit undef $scc
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S_BRANCH %bb.22
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bb.22:
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successors: %bb.23, %bb.24
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S_CBRANCH_SCC1 %bb.24, implicit undef $scc
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S_BRANCH %bb.23
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bb.23:
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bb.24:
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bb.25:
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bb.26:
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S_CBRANCH_SCC1 %bb.33, implicit undef $scc
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S_BRANCH %bb.27
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bb.27:
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S_CBRANCH_SCC1 %bb.33, implicit undef $scc
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S_BRANCH %bb.28
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bb.28:
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dead %77:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
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%78:vgpr_32 = nnan arcp contract reassoc nofpexcept V_MAD_F32 0, killed %113.sub1, 0, target-flags(amdgpu-gotprel32-lo) 0, 0, 1065353216, 0, 0, implicit $mode, implicit $exec
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dead %80:sreg_32_xm0 = S_MOV_B32 0
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dead %82:vgpr_32 = nofpexcept V_MUL_F32_e32 killed %78, %78, implicit $mode, implicit $exec
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dead %126:vgpr_32 = V_MOV_B32_e32 2143289344, implicit $exec
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dead %125:vreg_128 = IMPLICIT_DEF
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dead %91:sreg_32_xm0 = S_MOV_B32 2143289344
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%96:sreg_64 = S_AND_B64 $exec, 0, implicit-def dead $scc
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%139:vreg_128 = IMPLICIT_DEF
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bb.29:
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successors: %bb.30, %bb.31
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dead %127:vreg_128 = COPY killed %139
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S_CBRANCH_SCC0 %bb.31, implicit undef $scc
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bb.30:
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S_BRANCH %bb.32
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bb.31:
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successors: %bb.32, %bb.34
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$vcc = COPY %96
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S_CBRANCH_VCCNZ %bb.34, implicit killed $vcc
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S_BRANCH %bb.32
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bb.32:
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dead %130:vreg_128 = IMPLICIT_DEF
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dead %128:vreg_128 = COPY undef %130
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%139:vreg_128 = IMPLICIT_DEF
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S_BRANCH %bb.29
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bb.33:
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S_ENDPGM 0
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bb.34:
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S_ENDPGM 0
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...
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