c4d256a590
Detailed description:
After https://reviews.llvm.org/D59990 submit several issues were discovered.
Changes in common code were preserved but AMDGPU specific part was reverted to keep the backend working correctly.
Discovered issues were addressed in the following commits:
https://reviews.llvm.org/D67662
https://reviews.llvm.org/D67101
https://reviews.llvm.org/D63953
https://reviews.llvm.org/D63731
This change brings back AMDGPU specific changes.
Reviewed by: rampitec, arsenm
Differential Revision: https://reviews.llvm.org/D68635
llvm-svn: 374767
273 lines
13 KiB
LLVM
273 lines
13 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=VI -check-prefix=GCN %s
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declare float @llvm.fma.f32(float, float, float) #1
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declare double @llvm.fma.f64(double, double, double) #1
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declare float @llvm.fmuladd.f32(float, float, float) #1
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declare float @llvm.amdgcn.div.fixup.f32(float, float, float) #1
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; GCN-LABEL: {{^}}test_sgpr_use_twice_binop:
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; GCN: s_load_dword [[SGPR:s[0-9]+]],
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; GCN: v_add_f32_e64 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_binop(float addrspace(1)* %out, float %a) #0 {
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%dbl = fadd float %a, %a
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store float %dbl, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_three_ternary_op:
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; GCN: s_load_dword [[SGPR:s[0-9]+]],
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[SGPR]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_three_ternary_op(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_b:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], s[[SGPR0]], [[VGPR1]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_b(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float %b) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_use_s_v_s:
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SA:[0-9]+]]:[[SB:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; SI: buffer_load_dword [[VA0:v[0-9]+]]
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; SI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
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; GCN-NOT: v_mov_b32
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; VI: buffer_load_dword [[VA0:v[0-9]+]]
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; VI-NEXT: buffer_load_dword [[VA1:v[0-9]+]]
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; GCN-NOT: v_mov_b32
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; GCN: v_mov_b32_e32 [[VB:v[0-9]+]], s[[SB]]
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; GCN-NOT: v_mov_b32
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; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SA]], [[VA0]], [[VB]]
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; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SA]], [[VA1]], [[VB]]
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; GCN: buffer_store_dword [[RESULT0]]
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; GCN: buffer_store_dword [[RESULT1]]
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define amdgpu_kernel void @test_use_s_v_s(float addrspace(1)* %out, float %a, float %b, float addrspace(1)* %in) #0 {
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%va0 = load volatile float, float addrspace(1)* %in
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%va1 = load volatile float, float addrspace(1)* %in
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%fma0 = call float @llvm.fma.f32(float %a, float %va0, float %b) #1
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%fma1 = call float @llvm.fma.f32(float %a, float %va1, float %b) #1
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store volatile float %fma0, float addrspace(1)* %out
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store volatile float %fma1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_b_a:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], s[[SGPR0]], [[VGPR1]], s[[SGPR0]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_b_a(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %b, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_b_a_a:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR1]], s[[SGPR0]], s[[SGPR0]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_b_a_a(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma = call float @llvm.fma.f32(float %b, float %a, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_imm:
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; GCN: s_load_dword [[SGPR:s[0-9]+]]
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], 2.0
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_imm(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float 2.0) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_imm_a:
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; GCN: s_load_dword [[SGPR:s[0-9]+]]
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], 2.0, [[SGPR]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_imm_a(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float 2.0, float %a) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; Don't use fma since fma c, x, y is canonicalized to fma x, c, y
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_imm_a_a:
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; GCN: s_load_dword [[SGPR:s[0-9]+]]
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; GCN: v_div_fixup_f32 [[RESULT:v[0-9]+]], 2.0, [[SGPR]], [[SGPR]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_imm_a_a(float addrspace(1)* %out, float %a) #0 {
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%val = call float @llvm.amdgcn.div.fixup.f32(float 2.0, float %a, float %a) #1
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store float %val, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_sgpr_use_twice_ternary_op_a_a_kimm:
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; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VK:v[0-9]+]], 0x44800000
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[SGPR]], [[SGPR]], [[VK]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_sgpr_use_twice_ternary_op_a_a_kimm(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float %a, float 1024.0) #1
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store float %fma, float addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s:
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; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR]]
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; GCN: buffer_store_dword [[RESULT0]]
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1
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store float %fma, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_k_s_x2:
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR0]]
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; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[SK]], [[SK]], [[VGPR1]]
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; GCN: buffer_store_dword [[RESULT0]]
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; GCN: buffer_store_dword [[RESULT1]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_k_s_x2(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma0 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %a) #1
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%fma1 = call float @llvm.fma.f32(float 1024.0, float 1024.0, float %b) #1
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store volatile float %fma0, float addrspace(1)* %out
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store volatile float %fma1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k:
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; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1
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store float %fma, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_k_s_k_x2:
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
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; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]
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; GCN: buffer_store_dword [[RESULT0]]
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; GCN: buffer_store_dword [[RESULT1]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_k_s_k_x2(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma0 = call float @llvm.fma.f32(float 1024.0, float %a, float 1024.0) #1
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%fma1 = call float @llvm.fma.f32(float 1024.0, float %b, float 1024.0) #1
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store volatile float %fma0, float addrspace(1)* %out
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store volatile float %fma1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k:
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; GCN-DAG: s_load_dword [[SGPR:s[0-9]+]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
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; GCN: buffer_store_dword [[RESULT]]
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k(float addrspace(1)* %out, float %a) #0 {
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%fma = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1
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store float %fma, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_literal_use_twice_ternary_op_s_k_k_x2:
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]{{\:}}[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0xb|0x2c}}
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; GCN-DAG: v_mov_b32_e32 [[VGPR0:v[0-9]+]], s[[SGPR0]]
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; GCN-DAG: v_mov_b32_e32 [[VGPR1:v[0-9]+]], s[[SGPR1]]
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; GCN-DAG: s_mov_b32 [[SK:s[0-9]+]], 0x44800000
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; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], [[VGPR0]], [[SK]], [[SK]]
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; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], [[VGPR1]], [[SK]], [[SK]]
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; GCN: buffer_store_dword [[RESULT0]]
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; GCN: buffer_store_dword [[RESULT1]]
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; GCN: s_endpgm
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define amdgpu_kernel void @test_literal_use_twice_ternary_op_s_k_k_x2(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma0 = call float @llvm.fma.f32(float %a, float 1024.0, float 1024.0) #1
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%fma1 = call float @llvm.fma.f32(float %b, float 1024.0, float 1024.0) #1
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store volatile float %fma0, float addrspace(1)* %out
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store volatile float %fma1, float addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}test_s0_s1_k_f32:
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; SI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xb
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; VI-DAG: s_load_dwordx2 s{{\[}}[[SGPR0:[0-9]+]]:[[SGPR1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x2c
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; GCN-DAG: v_mov_b32_e32 [[VK0:v[0-9]+]], 0x44800000
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; GCN-DAG: v_mov_b32_e32 [[VS1:v[0-9]+]], s[[SGPR1]]
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; GCN-DAG: v_fma_f32 [[RESULT0:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK0]]
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; GCN-DAG: v_mov_b32_e32 [[VK1:v[0-9]+]], 0x45800000
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; GCN-DAG: v_fma_f32 [[RESULT1:v[0-9]+]], s[[SGPR0]], [[VS1]], [[VK1]]
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; GCN: buffer_store_dword [[RESULT0]]
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; GCN: buffer_store_dword [[RESULT1]]
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define amdgpu_kernel void @test_s0_s1_k_f32(float addrspace(1)* %out, float %a, float %b) #0 {
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%fma0 = call float @llvm.fma.f32(float %a, float %b, float 1024.0) #1
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%fma1 = call float @llvm.fma.f32(float %a, float %b, float 4096.0) #1
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store volatile float %fma0, float addrspace(1)* %out
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store volatile float %fma1, float addrspace(1)* %out
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ret void
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}
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; FIXME: Immediate in SGPRs just copied to VGPRs
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; GCN-LABEL: {{^}}test_s0_s1_k_f64:
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; GCN-DAG: s_load_dwordx2 [[SGPR0:s\[[0-9]+:[0-9]+\]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
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; GCN-DAG: s_load_dwordx2 s{{\[}}[[SGPR1_SUB0:[0-9]+]]:[[SGPR1_SUB1:[0-9]+]]{{\]}}, s{{\[[0-9]+:[0-9]+\]}}, {{0x1d|0x74}}
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; GCN-DAG: v_mov_b32_e32 v[[VK0_SUB1:[0-9]+]], 0x40900000
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; GCN-DAG: v_mov_b32_e32 v[[VZERO:[0-9]+]], 0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB0:[0-9]+]], s[[SGPR1_SUB0]]
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; GCN-DAG: v_mov_b32_e32 v[[VS1_SUB1:[0-9]+]], s[[SGPR1_SUB1]]
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; GCN: v_fma_f64 [[RESULT0:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK0_SUB1]]{{\]}}
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; Same zero component is re-used for half of each immediate.
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; GCN: v_mov_b32_e32 v[[VK1_SUB1:[0-9]+]], 0x40b00000
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; GCN: v_fma_f64 [[RESULT1:v\[[0-9]+:[0-9]+\]]], [[SGPR0]], v{{\[}}[[VS1_SUB0]]:[[VS1_SUB1]]{{\]}}, v{{\[}}[[VZERO]]:[[VK1_SUB1]]{{\]}}
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; GCN: buffer_store_dwordx2 [[RESULT0]]
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; GCN: buffer_store_dwordx2 [[RESULT1]]
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define amdgpu_kernel void @test_s0_s1_k_f64(double addrspace(1)* %out, [8 x i32], double %a, [8 x i32], double %b) #0 {
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%fma0 = call double @llvm.fma.f64(double %a, double %b, double 1024.0) #1
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%fma1 = call double @llvm.fma.f64(double %a, double %b, double 4096.0) #1
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store volatile double %fma0, double addrspace(1)* %out
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store volatile double %fma1, double addrspace(1)* %out
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ret void
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}
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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