62fd7f767c
tryLatency compares two sched candidates. For the top zone it prefers the one with lesser depth, but only if that depth is greater than the total latency of the instructions we've already scheduled -- otherwise its latency would be hidden and there would be no stall. Unfortunately it only tests the depth of one of the candidates. This can lead to situations where the TopDepthReduce heuristic does not kick in, but a lower priority heuristic chooses the other candidate, whose depth *is* greater than the already scheduled latency, which causes a stall. The fix is to apply the heuristic if the depth of *either* candidate is greater than the already scheduled latency. All this also applies to the BotHeightReduce heuristic in the bottom zone. Differential Revision: https://reviews.llvm.org/D72392
268 lines
9.1 KiB
LLVM
268 lines
9.1 KiB
LLVM
; RUN: llc -mcpu=pwr9 -mtriple=powerpc64le-unknown-unknown -ppc-vsr-nums-as-vr \
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; RUN: -verify-machineinstrs -ppc-asm-full-reg-names < %s | FileCheck %s
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; Function Attrs: norecurse nounwind readnone
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define fp128 @loadConstant() {
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; CHECK-LABEL: loadConstant:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI0_0@toc@ha
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; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI0_0@toc@l
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; CHECK-NEXT: lxvx v2, 0, r[[REG0]]
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; CHECK-NEXT: blr
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entry:
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ret fp128 0xL00000000000000004001400000000000
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}
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; Function Attrs: norecurse nounwind readnone
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define fp128 @loadConstant2(fp128 %a, fp128 %b) {
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; CHECK-LABEL: loadConstant2:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: addis r[[REG0:[0-9]+]], r2, .LCPI1_0@toc@ha
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; CHECK-NEXT: addi r[[REG0]], r[[REG0]], .LCPI1_0@toc@l
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; CHECK-NEXT: lxvx v[[REG1:[0-9]+]], 0, r[[REG0]]
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; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
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; CHECK-NEXT: blr
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entry:
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%add = fadd fp128 %a, %b
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%add1 = fadd fp128 %add, 0xL00000000000000004001400000000000
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ret fp128 %add1
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}
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; Test passing float128 by value.
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; Function Attrs: norecurse nounwind readnone
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define signext i32 @fp128Param(fp128 %a) {
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; CHECK-LABEL: fp128Param:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xscvqpswz v2, v2
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; CHECK-NEXT: mfvsrwz r3, v2
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; CHECK-NEXT: extsw r3, r3
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; CHECK-NEXT: blr
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entry:
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%conv = fptosi fp128 %a to i32
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ret i32 %conv
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}
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; Test float128 as return value.
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; Function Attrs: norecurse nounwind readnone
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define fp128 @fp128Return(fp128 %a, fp128 %b) {
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; CHECK-LABEL: fp128Return:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: blr
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entry:
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%add = fadd fp128 %a, %b
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ret fp128 %add
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}
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; array of float128 types
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; Function Attrs: norecurse nounwind readonly
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define fp128 @fp128Array(fp128* nocapture readonly %farray,
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; CHECK-LABEL: fp128Array:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: sldi r4, r4, 4
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; CHECK-NEXT: lxv v2, 0(r3)
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; CHECK-NEXT: add [[REG:r[0-9]+]], r3, r4
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; CHECK-NEXT: lxv v3, -16([[REG]])
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: blr
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i32 signext %loopcnt, fp128* nocapture readnone %sum) {
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entry:
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%0 = load fp128, fp128* %farray, align 16
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%sub = add nsw i32 %loopcnt, -1
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%idxprom = sext i32 %sub to i64
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%arrayidx1 = getelementptr inbounds fp128, fp128* %farray, i64 %idxprom
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%1 = load fp128, fp128* %arrayidx1, align 16
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%add = fadd fp128 %0, %1
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ret fp128 %add
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}
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; Up to 12 qualified floating-point arguments can be passed in v2-v13.
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; Function to test passing 13 float128 parameters.
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; Function Attrs: norecurse nounwind readnone
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define fp128 @maxVecParam(fp128 %p1, fp128 %p2, fp128 %p3, fp128 %p4, fp128 %p5,
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; CHECK-LABEL: maxVecParam:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: xsaddqp v2, v2, v3
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; CHECK-NEXT: lxv v[[REG0:[0-9]+]], 224(r1)
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; CHECK-NEXT: xsaddqp v2, v2, v4
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; CHECK-NEXT: xsaddqp v2, v2, v5
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; CHECK-NEXT: xsaddqp v2, v2, v6
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; CHECK-NEXT: xsaddqp v2, v2, v7
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; CHECK-NEXT: xsaddqp v2, v2, v8
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; CHECK-NEXT: xsaddqp v2, v2, v9
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; CHECK-NEXT: xsaddqp v2, v2, v10
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; CHECK-NEXT: xsaddqp v2, v2, v11
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; CHECK-NEXT: xsaddqp v2, v2, v12
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; CHECK-NEXT: xsaddqp v2, v2, v13
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; CHECK-NEXT: xssubqp v2, v2, v[[REG0]]
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; CHECK-NEXT: blr
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fp128 %p6, fp128 %p7, fp128 %p8, fp128 %p9, fp128 %p10,
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fp128 %p11, fp128 %p12, fp128 %p13) {
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entry:
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%add = fadd fp128 %p1, %p2
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%add1 = fadd fp128 %add, %p3
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%add2 = fadd fp128 %add1, %p4
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%add3 = fadd fp128 %add2, %p5
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%add4 = fadd fp128 %add3, %p6
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%add5 = fadd fp128 %add4, %p7
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%add6 = fadd fp128 %add5, %p8
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%add7 = fadd fp128 %add6, %p9
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%add8 = fadd fp128 %add7, %p10
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%add9 = fadd fp128 %add8, %p11
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%add10 = fadd fp128 %add9, %p12
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%sub = fsub fp128 %add10, %p13
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ret fp128 %sub
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}
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; Passing a mix of float128 and other type parameters.
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; Function Attrs: norecurse nounwind readnone
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define fp128 @mixParam_01(fp128 %a, i32 signext %i, fp128 %b) {
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; CHECK-LABEL: mixParam_01:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: mtvsrwa [[REG1:v[0-9]+]], r5
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; CHECK-DAG: xsaddqp v2, v2, v3
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; CHECK-NEXT: xscvsdqp v[[REG0:[0-9]+]], [[REG1]]
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; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
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; CHECK-NEXT: blr
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entry:
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%add = fadd fp128 %a, %b
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%conv = sitofp i32 %i to fp128
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%add1 = fadd fp128 %add, %conv
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ret fp128 %add1
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}
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; Function Attrs: norecurse nounwind readnone
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define fastcc fp128 @mixParam_01f(fp128 %a, i32 signext %i, fp128 %b) {
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; CHECK-LABEL: mixParam_01f:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r3
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; CHECK-DAG: xsaddqp v2, v2, v3
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; CHECK-NEXT: xscvsdqp v[[REG1:[0-9]+]], v[[REG0]]
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; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
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; CHECK-NEXT: blr
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entry:
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%add = fadd fp128 %a, %b
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%conv = sitofp i32 %i to fp128
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%add1 = fadd fp128 %add, %conv
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ret fp128 %add1
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}
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; Function Attrs: norecurse nounwind
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define fp128 @mixParam_02(fp128 %p1, double %p2, i64* nocapture %p3,
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; CHECK-LABEL: mixParam_02:
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; CHECK: # %bb.0: # %entry
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; CHECK: lwz r3, 96(r1)
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; CHECK: add r4, r7, r9
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; CHECK: xscpsgndp v[[REG0:[0-9]+]], f1, f1
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; CHECK: add r4, r4, r10
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; CHECK: xscvdpqp v[[REG0]], v[[REG0]]
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; CHECK: add r3, r4, r3
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; CHECK: clrldi r3, r3, 32
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; CHECK: std r3, 0(r6)
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; CHECK: lxv v[[REG1:[0-9]+]], 0(r8)
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; CHECK: xsaddqp v2, v[[REG1]], v2
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; CHECK: xsaddqp v2, v2, v3
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; CHECK-NEXT: blr
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i16 signext %p4, fp128* nocapture readonly %p5,
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i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
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entry:
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%conv = sext i16 %p4 to i32
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%add = add nsw i32 %conv, %p6
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%conv1 = zext i8 %p7 to i32
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%add2 = add nsw i32 %add, %conv1
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%add3 = add i32 %add2, %p8
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%conv4 = zext i32 %add3 to i64
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store i64 %conv4, i64* %p3, align 8
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%0 = load fp128, fp128* %p5, align 16
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%add5 = fadd fp128 %0, %p1
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%conv6 = fpext double %p2 to fp128
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%add7 = fadd fp128 %add5, %conv6
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ret fp128 %add7
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}
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; Function Attrs: norecurse nounwind
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define fastcc fp128 @mixParam_02f(fp128 %p1, double %p2, i64* nocapture %p3,
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; CHECK-LABEL: mixParam_02f:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: add r4, r4, r6
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; CHECK-NEXT: xscpsgndp v[[REG0:[0-9]+]], f1, f1
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; CHECK-NEXT: add r4, r4, r7
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; CHECK-NEXT: xscvdpqp v[[REG0]], v[[REG0]]
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; CHECK-NEXT: add r4, r4, r8
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; CHECK-NEXT: clrldi r4, r4, 32
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; CHECK-DAG: std r4, 0(r3)
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; CHECK-DAG: lxv v[[REG1:[0-9]+]], 0(r5)
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; CHECK-NEXT: xsaddqp v2, v[[REG1]], v2
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; CHECK-NEXT: xsaddqp v2, v2, v[[REG0]]
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; CHECK-NEXT: blr
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i16 signext %p4, fp128* nocapture readonly %p5,
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i32 signext %p6, i8 zeroext %p7, i32 zeroext %p8) {
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entry:
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%conv = sext i16 %p4 to i32
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%add = add nsw i32 %conv, %p6
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%conv1 = zext i8 %p7 to i32
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%add2 = add nsw i32 %add, %conv1
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%add3 = add i32 %add2, %p8
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%conv4 = zext i32 %add3 to i64
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store i64 %conv4, i64* %p3, align 8
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%0 = load fp128, fp128* %p5, align 16
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%add5 = fadd fp128 %0, %p1
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%conv6 = fpext double %p2 to fp128
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%add7 = fadd fp128 %add5, %conv6
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ret fp128 %add7
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}
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; Passing a mix of float128 and vector parameters.
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; Function Attrs: norecurse nounwind
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define void @mixParam_03(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
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; CHECK-LABEL: mixParam_03:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: ld r3, 104(r1)
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; CHECK-DAG: stxv v2, 0(r9)
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; CHECK: stxvx v3, 0, r3
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; CHECK: mtvsrwa v[[REG2:[0-9]+]], r10
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; CHECK-DAG: xscvsdqp v[[REG1:[0-9]+]], v[[REG2]]
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; CHECK-DAG: lxv v2, 0(r9)
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; CHECK-NEXT: xsaddqp v2, v2, v[[REG1]]
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; CHECK-NEXT: xscvqpdp v2, v2
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; CHECK-NEXT: stxsd v2, 0(r5)
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; CHECK-NEXT: blr
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fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
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<4 x i32>* nocapture %vec2) {
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entry:
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store fp128 %f1, fp128* %f2, align 16
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store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
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%0 = load fp128, fp128* %f2, align 16
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%conv = sitofp i32 %i1 to fp128
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%add = fadd fp128 %0, %conv
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%conv1 = fptrunc fp128 %add to double
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store double %conv1, double* %d1, align 8
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ret void
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}
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; Function Attrs: norecurse nounwind
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define fastcc void @mixParam_03f(fp128 %f1, double* nocapture %d1, <4 x i32> %vec1,
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; CHECK-LABEL: mixParam_03f:
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; CHECK: # %bb.0: # %entry
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; CHECK-DAG: mtvsrwa v[[REG0:[0-9]+]], r5
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; CHECK-DAG: stxv v[[REG1:[0-9]+]], 0(r4)
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; CHECK-DAG: stxv v[[REG2:[0-9]+]], 0(r7)
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; CHECK-DAG: lxv v[[REG1]], 0(r4)
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; CHECK-NEXT: xscvsdqp v[[REG3:[0-9]+]], v[[REG0]]
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; CHECK-NEXT: xsaddqp v[[REG4:[0-9]+]], v[[REG1]], v[[REG3]]
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; CHECK-NEXT: xscvqpdp v2, v[[REG4]]
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; CHECK-NEXT: stxsd v2, 0(r3)
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; CHECK-NEXT: blr
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fp128* nocapture %f2, i32 signext %i1, i8 zeroext %c1,
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<4 x i32>* nocapture %vec2) {
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entry:
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store fp128 %f1, fp128* %f2, align 16
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store <4 x i32> %vec1, <4 x i32>* %vec2, align 16
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%0 = load fp128, fp128* %f2, align 16
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%conv = sitofp i32 %i1 to fp128
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%add = fadd fp128 %0, %conv
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%conv1 = fptrunc fp128 %add to double
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store double %conv1, double* %d1, align 8
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ret void
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}
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