f92e0d9384
Change to not generate truncate instructions if all use of a truncate operation don't care about higher bits. For example, an i32 add instruction doesn't care about higher 32 bits in 64 bit registers. Updates regression tests also. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D85418
40 lines
1.0 KiB
LLVM
40 lines
1.0 KiB
LLVM
; RUN: llc < %s -mtriple=ve-unknown-unknown | FileCheck %s
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; Function Attrs: noinline nounwind optnone
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define dso_local i64 @bitcastd2l(double %x) {
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; CHECK-LABEL: bitcastd2l:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s11, 0, %s9
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%r = bitcast double %x to i64
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ret i64 %r
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}
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; Function Attrs: noinline nounwind optnone
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define dso_local double @bitcastl2d(i64 %x) {
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; CHECK-LABEL: bitcastl2d:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: or %s11, 0, %s9
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%r = bitcast i64 %x to double
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ret double %r
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}
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; Function Attrs: noinline nounwind optnone
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define dso_local float @bitcastw2f(i32 %x) {
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; CHECK-LABEL: bitcastw2f:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sll %s0, %s0, 32
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; CHECK-NEXT: or %s11, 0, %s9
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%r = bitcast i32 %x to float
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ret float %r
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}
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; Function Attrs: noinline nounwind optnone
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define dso_local i32 @bitcastf2w(float %x) {
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; CHECK-LABEL: bitcastf2w:
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; CHECK: .LBB{{[0-9]+}}_2:
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; CHECK-NEXT: sra.l %s0, %s0, 32
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; CHECK-NEXT: or %s11, 0, %s9
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%r = bitcast float %x to i32
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ret i32 %r
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}
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