b485586482
D82257/rG3521ecf1f8a3 was incorrectly sign-extending a constant vector from the lsb, this is fine if all the constant elements are 'allsignbits' in the active bits, but if only some of the elements are, then we are corrupting the constant values for those elements. This fix ensures we sign extend from the msb of the active/demanded bits instead.
25 lines
1.0 KiB
LLVM
25 lines
1.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE
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; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX
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; If targetShrinkDemandedConstant extends xor/or constants ensure it extends from the msb of the active bits
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define <4 x i32> @sext_vector_constants(<4 x i32> %a0) {
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; SSE-LABEL: sext_vector_constants:
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; SSE: # %bb.0:
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; SSE-NEXT: psrld $9, %xmm0
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; SSE-NEXT: pxor {{.*}}(%rip), %xmm0
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; SSE-NEXT: pslld $26, %xmm0
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; SSE-NEXT: retq
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;
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; AVX-LABEL: sext_vector_constants:
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; AVX: # %bb.0:
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; AVX-NEXT: vpsrld $9, %xmm0, %xmm0
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; AVX-NEXT: vpxor {{.*}}(%rip), %xmm0, %xmm0
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; AVX-NEXT: vpslld $26, %xmm0, %xmm0
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; AVX-NEXT: retq
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%1 = lshr <4 x i32> %a0, <i32 9, i32 9, i32 9, i32 9>
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%2 = xor <4 x i32> %1, <i32 314523200, i32 -2085372448, i32 144496960, i32 1532773600>
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%3 = shl <4 x i32> %2, <i32 26, i32 26, i32 26, i32 26>
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ret <4 x i32> %3
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}
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