4ba45a778a
Per the Vulkan's SPIR-V environment spec, "for the OpSRem and OpSMod instructions, if either operand is negative the result is undefined." So we cannot directly use spv.SRem/spv.SMod if either operand can be negative. Emulate it via spv.UMod. Because the emulation uses spv.SNegate, this commit also defines spv.SNegate. Differential Revision: https://reviews.llvm.org/D83679
85 lines
3.2 KiB
MLIR
85 lines
3.2 KiB
MLIR
// RUN: mlir-translate -test-spirv-roundtrip %s | FileCheck %s
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spv.module Logical GLSL450 requires #spv.vce<v1.0, [Shader], []> {
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spv.func @fmul(%arg0 : f32, %arg1 : f32) "None" {
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// CHECK: {{%.*}}= spv.FMul {{%.*}}, {{%.*}} : f32
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%0 = spv.FMul %arg0, %arg1 : f32
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spv.Return
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}
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spv.func @fadd(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FAdd {{%.*}}, {{%.*}} : vector<4xf32>
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%0 = spv.FAdd %arg0, %arg1 : vector<4xf32>
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spv.Return
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}
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spv.func @fdiv(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FDiv {{%.*}}, {{%.*}} : vector<4xf32>
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%0 = spv.FDiv %arg0, %arg1 : vector<4xf32>
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spv.Return
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}
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spv.func @fmod(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FMod {{%.*}}, {{%.*}} : vector<4xf32>
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%0 = spv.FMod %arg0, %arg1 : vector<4xf32>
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spv.Return
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}
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spv.func @fnegate(%arg0 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FNegate {{%.*}} : vector<4xf32>
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%0 = spv.FNegate %arg0 : vector<4xf32>
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spv.Return
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}
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spv.func @fsub(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FSub {{%.*}}, {{%.*}} : vector<4xf32>
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%0 = spv.FSub %arg0, %arg1 : vector<4xf32>
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spv.Return
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}
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spv.func @frem(%arg0 : vector<4xf32>, %arg1 : vector<4xf32>) "None" {
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// CHECK: {{%.*}} = spv.FRem {{%.*}}, {{%.*}} : vector<4xf32>
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%0 = spv.FRem %arg0, %arg1 : vector<4xf32>
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spv.Return
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}
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spv.func @iadd(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.IAdd {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.IAdd %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @isub(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.ISub {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.ISub %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @imul(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.IMul {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.IMul %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @udiv(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.UDiv {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.UDiv %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @umod(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.UMod {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.UMod %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @sdiv(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.SDiv {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.SDiv %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @smod(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.SMod {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.SMod %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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spv.func @snegate(%arg0 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.SNegate {{%.*}} : vector<4xi32>
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%0 = spv.SNegate %arg0 : vector<4xi32>
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spv.Return
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}
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spv.func @srem(%arg0 : vector<4xi32>, %arg1 : vector<4xi32>) "None" {
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// CHECK: {{%.*}} = spv.SRem {{%.*}}, {{%.*}} : vector<4xi32>
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%0 = spv.SRem %arg0, %arg1 : vector<4xi32>
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spv.Return
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}
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}
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