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llvm-project/llvm/lib/Target/VE
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Akshay Deodhar 3860147a7f
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073) 
Splits out change from https://github.com/llvm/llvm-project/pull/176015

Changes shouldExpandAtomicRMWInIR to take a constant argument: This is
to allow some other TargetLowering constant-argument functions to call
it. This change touches several backends. An alternative solution
exists, but to me, this seems the "right" way.
2026-01-15 14:22:57 -08:00
..
AsmParser
Fixes non-functional changes found static analyzer (#171197)
2025-12-12 20:03:02 +01:00
Disassembler
[Target] Add "override" where appropriate (NFC) (#165083)
2025-10-25 06:23:43 -07:00
MCTargetDesc
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TargetInfo
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CMakeLists.txt
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
LVLGen.cpp
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VE.h
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VE.td
CodeGen: Make all targets override pseudos with pointers (#159881)
2025-11-26 14:57:14 +00:00
VEAsmPrinter.cpp
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VECallingConv.td
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VECustomDAG.cpp
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VECustomDAG.h
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VEFrameLowering.cpp
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VEFrameLowering.h
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VEInstrBuilder.h
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VEInstrFormats.td
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VEInstrInfo.cpp
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)
2026-01-13 08:21:58 +05:30
VEInstrInfo.h
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload (#175581)
2026-01-13 08:21:58 +05:30
VEInstrInfo.td
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VEInstrIntrinsicVL.gen.td
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VEInstrIntrinsicVL.td
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VEInstrPatternsVec.td
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VEInstrVec.td
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VEISelDAGToDAG.cpp
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VEISelLowering.cpp
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073)
2026-01-15 14:22:57 -08:00
VEISelLowering.h
[NFC][TargetLowering] Make shouldExpandAtomicRMWInIR and shouldExpandAtomicCmpXchgInIR take a const Instruction pointer (#176073)
2026-01-15 14:22:57 -08:00
VEMachineFunctionInfo.cpp
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VEMachineFunctionInfo.h
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VEMCInstLower.cpp
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VERegisterInfo.cpp
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VERegisterInfo.h
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VERegisterInfo.td
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VESelectionDAGInfo.cpp
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VESelectionDAGInfo.h
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VESubtarget.cpp
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VESubtarget.h
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VETargetMachine.cpp
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VETargetMachine.h
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VETargetTransformInfo.h
[NVPTX] Lower LLVM masked vector loads and stores to PTX (#159387)
2025-11-25 10:26:15 -06:00
VVPInstrInfo.td
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VVPInstrPatternsVec.td
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VVPISelLowering.cpp
[VE] TableGen-erate SDNode descriptions (#168120)
2025-11-14 22:05:57 +00:00
VVPNodes.def
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