44b94a4f75
This patch adds the target hooks required by Instruction Referencing for the AArch64 target, as mentioned in https://llvm.org/docs/InstrRefDebugInfo.html#target-hooks Which allows the Instruction Referenced LiveDebugValues Pass to track spills and restore instructions. With this patch we can use the `llvm/utils/llvm-locstats/llvm-locstats.py` to see the coverage statistics on a clang.dSYM built with in RelWithDebInfo we can see: coverage with dbg_value: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5828021 38% (0%,10%) 127739 0% [10%,20%) 143344 0% [20%,30%) 172100 1% [30%,40%) 193173 1% [40%,50%) 127366 0% [50%,60%) 308350 2% [60%,70%) 257055 1% [70%,80%) 212410 1% [80%,90%) 295316 1% [90%,100%) 349280 2% 100% 7313157 47% ================================================= -the number of debug variables processed: 15327311 -PC ranges covered: 67% ------------------------------------------------- -total availability: 62% ================================================= ``` coverage with InstrRef without target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 6052807 39% (0%,10%) 127710 0% [10%,20%) 129999 0% [20%,30%) 155011 1% [30%,40%) 171206 1% [40%,50%) 102861 0% [50%,60%) 264734 1% [60%,70%) 212386 1% [70%,80%) 176872 1% [80%,90%) 242120 1% [90%,100%) 254465 1% 100% 7437215 48% ================================================= -the number of debug variables processed: 15327386 -PC ranges covered: 67% ------------------------------------------------- -total availability: 60% ================================================= ``` coverage with InstrRef with target hooks fix: ``` ================================================= Debug Location Statistics ================================================= cov% samples percentage(~) ------------------------------------------------- 0% 5972267 39% (0%,10%) 118873 0% [10%,20%) 127138 0% [20%,30%) 153181 1% [30%,40%) 170102 1% [40%,50%) 102180 0% [50%,60%) 263672 1% [60%,70%) 212865 1% [70%,80%) 176633 1% [80%,90%) 242403 1% [90%,100%) 264441 1% 100% 7494527 48% ================================================= -the number of debug variables processed: 15298282 -PC ranges covered: 71% ------------------------------------------------- -total availability: 61% ================================================= ``` I believe this should be a good indication that Instruction Referencing should be turned on for AArch64?
58 lines
2.5 KiB
LLVM
58 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK0
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -aarch64-stack-hazard-size=1024 | FileCheck %s --check-prefix=CHECK1024
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;; The following run lines check the default values for aarch64-stack-hazard-size/aarch64-streaming-hazard-size.
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;; When +sme,+sve is set the hazard size should default to 1024.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK1024
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;; The hazard size can still be overridden/disabled when +sme,+sve is set.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme -mattr=+sve -aarch64-stack-hazard-size=0 | FileCheck %s --check-prefix=CHECK0
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;; When +sme-fa64 is set alongside +sme,+sve the default hazard size should be 0.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme-fa64 -mattr=+sme -mattr=+sve | FileCheck %s --check-prefix=CHECK0
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;; When +sme is set (without +sve) the default hazard size should be 0.
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; RUN: llc < %s -mtriple=aarch64 -mattr=+sme | FileCheck %s --check-prefix=CHECK0
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define i32 @spill_fpr_with_gpr_stack_object(i64 %d) "aarch64_pstate_sm_compatible" {
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; CHECK0-LABEL: spill_fpr_with_gpr_stack_object:
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; CHECK0: // %bb.0: // %entry
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; CHECK0-NEXT: str d8, [sp, #-16]! // 8-byte Folded Spill
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; CHECK0-NEXT: .cfi_def_cfa_offset 16
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; CHECK0-NEXT: .cfi_offset b8, -16
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; CHECK0-NEXT: mov x8, x0
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; CHECK0-NEXT: mov w0, wzr
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; CHECK0-NEXT: //APP
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; CHECK0-NEXT: //NO_APP
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; CHECK0-NEXT: str x8, [sp, #8]
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; CHECK0-NEXT: ldr d8, [sp], #16 // 8-byte Folded Reload
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; CHECK0-NEXT: ret
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;
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; CHECK1024-LABEL: spill_fpr_with_gpr_stack_object:
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; CHECK1024: // %bb.0: // %entry
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; CHECK1024-NEXT: sub sp, sp, #1040
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; CHECK1024-NEXT: str d8, [sp] // 8-byte Spill
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; CHECK1024-NEXT: str x29, [sp, #1032] // 8-byte Spill
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; CHECK1024-NEXT: sub sp, sp, #1040
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; CHECK1024-NEXT: .cfi_def_cfa_offset 2080
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; CHECK1024-NEXT: .cfi_offset w29, -8
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; CHECK1024-NEXT: .cfi_offset b8, -1040
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; CHECK1024-NEXT: mov x8, x0
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; CHECK1024-NEXT: mov w0, wzr
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; CHECK1024-NEXT: //APP
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; CHECK1024-NEXT: //NO_APP
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; CHECK1024-NEXT: str x8, [sp, #8]
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; CHECK1024-NEXT: add sp, sp, #1040
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; CHECK1024-NEXT: ldr x29, [sp, #1032] // 8-byte Reload
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; CHECK1024-NEXT: ldr d8, [sp] // 8-byte Reload
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; CHECK1024-NEXT: add sp, sp, #1040
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; CHECK1024-NEXT: ret
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entry:
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%a = alloca i64
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tail call void asm sideeffect "", "~{d8}"() #1
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store i64 %d, ptr %a
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ret i32 0
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}
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