shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
Matt Arsenault 2502e3b7ba
IR: Promote "denormal-fp-math" to a first class attribute (#174293) 
Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first
class denormal_fpenv attribute. Previously the query for the effective
denormal mode involved two string attribute queries with parsing. I'm
introducing more uses of this, so it makes sense to convert this
to a more efficient encoding. The old representation was also awkward
since it was split across two separate attributes. The new encoding
just stores the default and float modes as bitfields, largely avoiding
the need to consider if the other mode is set.

The syntax in the common cases looks like this:
  `denormal_fpenv(preservesign,preservesign)`
  `denormal_fpenv(float: preservesign,preservesign)`
  `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)`

I wasn't sure about reusing the float type name instead of adding a
new keyword. It's parsed as a type but only accepts float. I'm also
debating switching the name to subnormal to match the current
preferred IEEE terminology (also used by nofpclass and other
contexts).

This has a behavior change when using the command flag debug
options to set the denormal mode. The behavior of the flag
ignored functions with an explicit attribute set, per
the default and f32 version. Now that these are one attribute,
the flag logic can't distinguish which of the two components
were explicitly set on the function. Only one test appeared to
rely on this behavior, so I just avoided using the flags in it.

This also does not perform all the code cleanups this enables.
In particular the attributor handling could be cleaned up.

I also guessed at how to support this in MLIR. I followed
MemoryEffects as a reference; it appears bitfields are expanded
into arguments to attributes, so the representation there is
a bit uglier with the 2 2-element fields flattened into 4 arguments.
2026-02-05 13:31:26 +00:00

223 lines
7.8 KiB
LLVM
Raw Blame History

; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_on:
; GCN: v_mul_f32_e64 [[QUIET0:v[0-9]+]], 1.0, s{{[0-9]+}}
; GCN: v_mul_f32_e64 [[QUIET1:v[0-9]+]], 1.0, s{{[0-9]+}}
; GCN: v_max_f32_e32 [[RESULT:v[0-9]+]], [[QUIET1]], [[QUIET0]]
; GCN-NOT: [[RESULT]]
; GCN: buffer_store_dword [[RESULT]]
define amdgpu_kernel void @test_fmax_f32_ieee_mode_on(ptr addrspace(1) %out, float %a, float %b) #0 {
%val = call float @llvm.maxnum.f32(float %a, float %b) #1
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}test_fmax_f32_ieee_mode_off:
; GCN: v_max_f32_e32 v0, v0, v1
; GCN-NEXT: ; return
define amdgpu_ps float @test_fmax_f32_ieee_mode_off(float %a, float %b) #0 {
%val = call float @llvm.maxnum.f32(float %a, float %b) #1
ret float %val
}
; GCN-LABEL: {{^}}test_fmax_v2f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
%val = call <2 x float> @llvm.maxnum.v2f32(<2 x float> %a, <2 x float> %b)
store <2 x float> %val, ptr addrspace(1) %out, align 8
ret void
}
; GCN-LABEL: {{^}}test_fmax_v3f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN-NOT: v_max_f32
define amdgpu_kernel void @test_fmax_v3f32(ptr addrspace(1) %out, <3 x float> %a, <3 x float> %b) nounwind {
%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b)
store <3 x float> %val, ptr addrspace(1) %out, align 16
ret void
}
; GCN-LABEL: {{^}}test_fmax_v4f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v4f32(ptr addrspace(1) %out, <4 x float> %a, <4 x float> %b) #0 {
%val = call <4 x float> @llvm.maxnum.v4f32(<4 x float> %a, <4 x float> %b)
store <4 x float> %val, ptr addrspace(1) %out, align 16
ret void
}
; GCN-LABEL: {{^}}test_fmax_v8f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v8f32(ptr addrspace(1) %out, <8 x float> %a, <8 x float> %b) #0 {
%val = call <8 x float> @llvm.maxnum.v8f32(<8 x float> %a, <8 x float> %b)
store <8 x float> %val, ptr addrspace(1) %out, align 32
ret void
}
; GCN-LABEL: {{^}}test_fmax_v16f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
define amdgpu_kernel void @test_fmax_v16f32(ptr addrspace(1) %out, <16 x float> %a, <16 x float> %b) #0 {
%val = call <16 x float> @llvm.maxnum.v16f32(<16 x float> %a, <16 x float> %b)
store <16 x float> %val, ptr addrspace(1) %out, align 64
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 2.0
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 1.0, float 2.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_nan:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x7fc00000
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_nan_nan(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_val_nan:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_val_nan(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 1.0, float 0x7FF8000000000000)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_nan_val:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 1.0
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_nan_val(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 0x7FF8000000000000, float 1.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_p0:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_p0_p0(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_p0_n0:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_p0_n0(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float 0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_p0:
; GCN-NOT: v_max_f32_e32
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0{{$}}
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_n0_p0(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float -0.0, float 0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}constant_fold_fmax_f32_n0_n0:
; GCN-NOT: v_max_f32_e32
; GCN: v_bfrev_b32_e32 [[REG:v[0-9]+]], 1{{$}}
; GCN: buffer_store_dword [[REG]]
define amdgpu_kernel void @constant_fold_fmax_f32_n0_n0(ptr addrspace(1) %out) #0 {
%val = call float @llvm.maxnum.f32(float -0.0, float -0.0)
store float %val, ptr addrspace(1) %out, align 4
ret void
}
; GCN-LABEL: {{^}}fmax_var_immediate_f32_no_ieee:
; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
define amdgpu_ps float @fmax_var_immediate_f32_no_ieee(float inreg %a) #0 {
%val = call float @llvm.maxnum.f32(float %a, float 2.0)
ret float %val
}
; GCN-LABEL: {{^}}fmax_immediate_var_f32_no_ieee:
; GCN: v_max_f32_e64 {{v[0-9]+}}, {{s[0-9]+}}, 2.0
define amdgpu_ps float @fmax_immediate_var_f32_no_ieee(float inreg %a) #0 {
%val = call float @llvm.maxnum.f32(float 2.0, float %a)
ret float %val
}
; GCN-LABEL: {{^}}fmax_var_literal_f32_no_ieee:
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmax_var_literal_f32_no_ieee(float inreg %a) #0 {
%val = call float @llvm.maxnum.f32(float %a, float 99.0)
ret float %val
}
; GCN-LABEL: {{^}}fmax_literal_var_f32_no_ieee:
; GCN: v_mov_b32_e32 [[REG:v[0-9]+]], 0x42c60000
; GCN: v_max_f32_e32 {{v[0-9]+}}, {{s[0-9]+}}, [[REG]]
define amdgpu_ps float @fmax_literal_var_f32_no_ieee(float inreg %a) #0 {
%val = call float @llvm.maxnum.f32(float 99.0, float %a)
ret float %val
}
; GCN-LABEL: {{^}}test_func_fmax_v3f32:
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN: v_max_f32_e32
; GCN-NOT: v_max_f32
define <3 x float> @test_func_fmax_v3f32(<3 x float> %a, <3 x float> %b) #0 {
%val = call <3 x float> @llvm.maxnum.v3f32(<3 x float> %a, <3 x float> %b)
ret <3 x float> %val
}
declare float @llvm.maxnum.f32(float, float) #1
declare <2 x float> @llvm.maxnum.v2f32(<2 x float>, <2 x float>) #1
declare <3 x float> @llvm.maxnum.v3f32(<3 x float>, <3 x float>) #1
declare <4 x float> @llvm.maxnum.v4f32(<4 x float>, <4 x float>) #1
declare <8 x float> @llvm.maxnum.v8f32(<8 x float>, <8 x float>) #1
declare <16 x float> @llvm.maxnum.v16f32(<16 x float>, <16 x float>) #1
declare double @llvm.maxnum.f64(double, double)
attributes #0 = { nounwind denormal_fpenv(float: preservesign) }
attributes #1 = { nounwind readnone }
Reference in New Issue View Git Blame Copy Permalink