2502e3b7ba
Convert "denormal-fp-math" and "denormal-fp-math-f32" into a first class denormal_fpenv attribute. Previously the query for the effective denormal mode involved two string attribute queries with parsing. I'm introducing more uses of this, so it makes sense to convert this to a more efficient encoding. The old representation was also awkward since it was split across two separate attributes. The new encoding just stores the default and float modes as bitfields, largely avoiding the need to consider if the other mode is set. The syntax in the common cases looks like this: `denormal_fpenv(preservesign,preservesign)` `denormal_fpenv(float: preservesign,preservesign)` `denormal_fpenv(dynamic,dynamic float: preservesign,preservesign)` I wasn't sure about reusing the float type name instead of adding a new keyword. It's parsed as a type but only accepts float. I'm also debating switching the name to subnormal to match the current preferred IEEE terminology (also used by nofpclass and other contexts). This has a behavior change when using the command flag debug options to set the denormal mode. The behavior of the flag ignored functions with an explicit attribute set, per the default and f32 version. Now that these are one attribute, the flag logic can't distinguish which of the two components were explicitly set on the function. Only one test appeared to rely on this behavior, so I just avoided using the flags in it. This also does not perform all the code cleanups this enables. In particular the attributor handling could be cleaned up. I also guessed at how to support this in MLIR. I followed MemoryEffects as a reference; it appears bitfields are expanded into arguments to attributes, so the representation there is a bit uglier with the 2 2-element fields flattened into 4 arguments.
172 lines
5.4 KiB
LLVM
172 lines
5.4 KiB
LLVM
; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s
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; RUN: llc -mtriple=amdgcn -mcpu=tahiti -early-live-intervals < %s | FileCheck %s
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; CHECK-LABEL: {{^}}fold_sgpr:
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; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s
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define amdgpu_kernel void @fold_sgpr(ptr addrspace(1) %out, i32 %fold) #1 {
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entry:
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%tmp0 = icmp ne i32 %fold, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%offset = add i32 %fold, %id
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%tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %offset
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store i32 0, ptr addrspace(1) %tmp1
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_imm:
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; CHECK: v_or_b32_e32 v{{[0-9]+}}, 5
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define amdgpu_kernel void @fold_imm(ptr addrspace(1) %out, i32 %cmp) #1 {
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entry:
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%fold = add i32 3, 2
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%tmp0 = icmp ne i32 %cmp, 0
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br i1 %tmp0, label %if, label %endif
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if:
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%id = call i32 @llvm.amdgcn.workitem.id.x()
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%val = or i32 %id, %fold
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store i32 %val, ptr addrspace(1) %out
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br label %endif
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endif:
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ret void
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}
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; CHECK-LABEL: {{^}}fold_64bit_constant_add:
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; CHECK-NOT: s_mov_b64
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; FIXME: It would be better if we could use v_add here and drop the extra
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; v_mov_b32 instructions.
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; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 1
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; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 0
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; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]
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; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]
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; CHECK: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]],
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define amdgpu_kernel void @fold_64bit_constant_add(ptr addrspace(1) %out, i32 %cmp, i64 %val) #1 {
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entry:
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%tmp0 = add i64 %val, 1
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store i64 %tmp0, ptr addrspace(1) %out
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ret void
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}
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; Inline constants should always be folded.
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; CHECK-LABEL: {{^}}vector_inline:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}
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define amdgpu_kernel void @vector_inline(ptr addrspace(1) %out) #1 {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec3
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store <4 x i32> %tmp4, ptr addrspace(1) %out
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ret void
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}
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; Immediates with one use should be folded
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; CHECK-LABEL: {{^}}imm_one_use:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}
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define amdgpu_kernel void @imm_one_use(ptr addrspace(1) %out) #1 {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = xor i32 %tmp0, 100
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; CHECK-LABEL: {{^}}vector_imm:
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
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; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}
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define amdgpu_kernel void @vector_imm(ptr addrspace(1) %out) #1 {
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entry:
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%tmp0 = call i32 @llvm.amdgcn.workitem.id.x()
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%tmp1 = add i32 %tmp0, 1
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%tmp2 = add i32 %tmp0, 2
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%tmp3 = add i32 %tmp0, 3
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%vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0
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%vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1
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%vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2
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%vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3
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%tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3
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store <4 x i32> %tmp4, ptr addrspace(1) %out
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ret void
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}
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; A subregister use operand should not be tied.
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; CHECK-LABEL: {{^}}no_fold_tied_subregister:
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; CHECK: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; CHECK: v_madmk_f32 v[[RES:[0-9]+]], v[[HI]], 0x41200000, v[[LO]]
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; CHECK: buffer_store_dword v[[RES]]
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define amdgpu_kernel void @no_fold_tied_subregister() #1 {
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%tmp1 = load volatile <2 x float>, ptr addrspace(1) poison
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%tmp2 = extractelement <2 x float> %tmp1, i32 0
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%tmp3 = extractelement <2 x float> %tmp1, i32 1
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%tmp4 = fmul float %tmp3, 10.0
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%tmp5 = fadd float %tmp4, %tmp2
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store volatile float %tmp5, ptr addrspace(1) poison
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ret void
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}
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; There should be exact one folding on the same operand.
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; CHECK-LABEL: {{^}}no_extra_fold_on_same_opnd
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; CHECK-NOT: %bb.1:
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; CHECK: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
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define void @no_extra_fold_on_same_opnd() #1 {
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entry:
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%s0 = load i32, ptr addrspace(5) poison, align 4
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%s0.i64= zext i32 %s0 to i64
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br label %for.body.i.i
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for.body.i.i:
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%s1 = load i32, ptr addrspace(1) poison, align 8
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%s1.i64 = sext i32 %s1 to i64
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%xor = xor i64 %s1.i64, %s0.i64
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%flag = icmp ult i64 %xor, 8
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br i1 %flag, label %if.then, label %if.else
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if.then:
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unreachable
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if.else:
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unreachable
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}
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; The compared constant is equal to {42, 42}. It cannot be reduced to
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; a compare with 42.
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define i32 @issue139908(i64 %in) {
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; CHECK-LABEL: issue139908:
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; CHECK: ; %bb.0:
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; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; CHECK-NEXT: s_mov_b32 s4, 42
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; CHECK-NEXT: s_mov_b32 s5, s4
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; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]
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; CHECK-NEXT: v_cndmask_b32_e64 v0, 2, 1, vcc
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; CHECK-NEXT: s_setpc_b64 s[30:31]
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%eq = icmp eq i64 %in, 180388626474
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%result = select i1 %eq, i32 1, i32 2
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ret i32 %result
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #0
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attributes #0 = { nounwind readnone }
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attributes #1 = { nounwind denormal_fpenv(float: preservesign) }
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