ff13189c5d
How many place you need to modify when implementing a new extension for RISC-V? At least 7 places as I know: - Add new SubtargetFeature at RISCV.td - -march parser in RISCV.cpp - RISCVTargetInfo::initFeatureMap@RISCV.cpp for handling feature vector. - RISCVTargetInfo::getTargetDefines@RISCV.cpp for pre-define marco. - Arch string parser for ELF attribute in RISCVAsmParser.cpp - ELF attribute emittion in RISCVAsmParser.cpp, and make sure it's in canonical order... - ELF attribute emittion in RISCVTargetStreamer.cpp, and again, must in canonical order... And now, this patch provide an unified infrastructure for handling (almost) everything of RISC-V arch string. After this patch, you only need to update 2 places for implement an extension for RISC-V: - Add new SubtargetFeature at RISCV.td, hmmm, it's hard to avoid. - Add new entry to RISCVSupportedExtension@RISCVISAInfo.cpp or SupportedExperimentalExtensions@RISCVISAInfo.cpp . Most codes are come from existing -march parser, but with few new feature/bug fixes: - Accept version for -march, e.g. -march=rv32i2p0. - Reject version info with `p` but without minor version number like `rv32i2p`. Differential Revision: https://reviews.llvm.org/D105168
114 lines
4.1 KiB
C++
114 lines
4.1 KiB
C++
//===-- RISCVTargetStreamer.cpp - RISCV Target Streamer Methods -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file provides RISCV specific target streamer methods.
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//
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//===----------------------------------------------------------------------===//
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#include "RISCVTargetStreamer.h"
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#include "RISCVBaseInfo.h"
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#include "RISCVMCTargetDesc.h"
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#include "llvm/Support/FormattedStream.h"
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#include "llvm/Support/RISCVAttributes.h"
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#include "llvm/Support/RISCVISAInfo.h"
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using namespace llvm;
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RISCVTargetStreamer::RISCVTargetStreamer(MCStreamer &S) : MCTargetStreamer(S) {}
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void RISCVTargetStreamer::finish() { finishAttributeSection(); }
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void RISCVTargetStreamer::emitDirectiveOptionPush() {}
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void RISCVTargetStreamer::emitDirectiveOptionPop() {}
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void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
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void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
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void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
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void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
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void RISCVTargetStreamer::finishAttributeSection() {}
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void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {}
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void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
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if (STI.hasFeature(RISCV::FeatureRV32E))
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emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_4);
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else
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emitAttribute(RISCVAttrs::STACK_ALIGN, RISCVAttrs::ALIGN_16);
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unsigned XLen = STI.hasFeature(RISCV::Feature64Bit) ? 64 : 32;
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std::vector<std::string> FeatureVector;
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RISCVFeatures::toFeatureVector(FeatureVector, STI.getFeatureBits());
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auto ParseResult = llvm::RISCVISAInfo::parseFeatures(XLen, FeatureVector);
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if (!ParseResult) {
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/* Assume any error about features should handled earlier. */
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consumeError(ParseResult.takeError());
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llvm_unreachable("Parsing feature error when emitTargetAttributes?");
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} else {
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auto &ISAInfo = *ParseResult;
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emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString());
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}
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}
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// This part is for ascii assembly output
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RISCVTargetAsmStreamer::RISCVTargetAsmStreamer(MCStreamer &S,
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formatted_raw_ostream &OS)
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: RISCVTargetStreamer(S), OS(OS) {}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPush() {
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OS << "\t.option\tpush\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPop() {
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OS << "\t.option\tpop\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionPIC() {
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OS << "\t.option\tpic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoPIC() {
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OS << "\t.option\tnopic\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRVC() {
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OS << "\t.option\trvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRVC() {
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OS << "\t.option\tnorvc\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
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OS << "\t.option\trelax\n";
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}
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void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
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OS << "\t.option\tnorelax\n";
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}
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void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
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OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
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}
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void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {
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OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
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}
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void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void RISCVTargetAsmStreamer::finishAttributeSection() {}
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