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llvm-project/llvm/lib/Target/RISCV
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Zakk Chen 9ab18cc535 [RISCV] Add policy operand for masked vid and viota IR intrinsics. 
Reviewed By: rogfer01

Differential Revision: https://reviews.llvm.org/D120227
2022-03-22 02:32:31 -07:00
..
AsmParser
[RISCV] add the MC layer support of Zfinx extension
2022-03-02 14:25:19 +08:00
Disassembler
[RISCV] add the MC layer support of Zfinx extension
2022-03-02 14:25:19 +08:00
MCTargetDesc
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
TargetInfo
…
CMakeLists.txt
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCV.h
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCV.td
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
RISCVAsmPrinter.cpp
…
RISCVCallingConv.td
…
RISCVCallLowering.cpp
…
RISCVCallLowering.h
…
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVExpandPseudoInsts.cpp
[RISCV] Update comments about getInstSizeInBytes hard-coding the number of bytes.
2022-01-28 09:51:49 -08:00
RISCVFrameLowering.cpp
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
RISCVFrameLowering.h
Revert "[RISCV] Enable shrink wrap by default"
2022-02-12 19:04:12 +01:00
RISCVGatherScatterLowering.cpp
[RISCV] Teach RISCVGatherScatterLowering to handle more complex recurrence start values.
2022-01-04 10:13:34 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormats.td
[RISCV] Support mask policy for RVV IR intrinsics.
2022-03-22 01:19:16 -07:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
[RISCV] Remove Zvamo Extention
2021-12-20 10:28:39 +08:00
RISCVInstrInfo.cpp
Revert "[RISCV] LUI used for address computation should not isAsCheapAsAMove"
2022-02-17 17:27:37 +08:00
RISCVInstrInfo.h
[MachineOutliner] NFC: Hide LRU-related stuff behind helper functions
2022-02-16 11:39:07 -08:00
RISCVInstrInfo.td
[RISCV] Ensure PseudoLA* can be hoisted
2022-03-16 18:45:36 +00:00
RISCVInstrInfoA.td
[RISCV] Change GPRMemAtomic to GPRMemZeroOffset for general usage
2022-02-28 14:02:43 +08:00
RISCVInstrInfoC.td
…
RISCVInstrInfoD.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoF.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
[RISCV] Change rvv version to 1.0 and remove ratify notice
2022-02-25 11:38:20 +11:00
RISCVInstrInfoVPseudos.td
[RISCV] Add policy operand for masked vid and viota IR intrinsics.
2022-03-22 02:32:31 -07:00
RISCVInstrInfoVSDPatterns.td
[RISCV] Fold store of vmv.f.s to a vse with VL=1.
2022-03-03 16:35:19 +08:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Add patterns for vnsrl.wi and vnsra.wi instructions
2022-03-17 07:22:32 +00:00
RISCVInstrInfoZb.td
[RISCV] Move GORCIW/GREVIW formation to isel patterns.
2022-03-11 18:02:47 -08:00
RISCVInstrInfoZfh.td
[RISCV] Share PatFprFpr classes for F, D, and Zfh
2022-03-08 13:02:04 +08:00
RISCVInstrInfoZk.td
[RISCV] Adjust some comments.
2022-02-01 22:53:54 +08:00
RISCVInstructionSelector.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Improve detection of when to skip (and (srl x, c2) c1) -> (srli (slli x, c3-c2), c3) isel.
2022-03-16 14:54:34 -07:00
RISCVISelDAGToDAG.h
[RISCV] Select unmasked RVV pseudos in a DAG post-process
2022-02-09 07:50:15 +00:00
RISCVISelLowering.cpp
Revert "[RISCV] Special case sign extended scalars when type legalizing nxvXi64 .vx instrinsics on RV32."
2022-03-21 14:58:11 -07:00
RISCVISelLowering.h
[RISCV][RVV] Fix vslide1up/down intrinsics overflow bug for SEW=64 on RV32
2022-03-13 18:06:09 +08:00
RISCVLegalizerInfo.cpp
…
RISCVLegalizerInfo.h
…
RISCVMachineFunctionInfo.h
…
RISCVMCInstLower.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
RISCVMergeBaseOffset.cpp
[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated comments
2022-03-16 20:25:42 +08:00
RISCVRedundantCopyElimination.cpp
[RISCV] Implement a basic version of AArch64RedundantCopyElimination pass.
2022-02-04 10:43:46 -08:00
RISCVRegisterBankInfo.cpp
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBankInfo.h
[nfc][codegen] Move RegisterBank[Info].h under CodeGen
2022-03-01 21:53:25 -08:00
RISCVRegisterBanks.td
…
RISCVRegisterInfo.cpp
Drop some more global std::maps. NFCI.
2022-03-06 13:28:29 +01:00
RISCVRegisterInfo.h
[RISCV] Set CostPerUse to 1 iff RVC is enabled
2022-01-21 14:44:26 +08:00
RISCVRegisterInfo.td
[RISCV] add the MC layer support of Zfinx extension
2022-03-02 14:25:19 +08:00
RISCVSchedRocket.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedSiFive7.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVSchedule.td
…
RISCVScheduleB.td
[RISCV] Add schedule class for Zbp extension and Zbr extension
2022-03-01 07:35:59 +00:00
RISCVScheduleV.td
…
RISCVSExtWRemoval.cpp
[RISCV] Add more sign-extending ops to MIR sext.w pass.
2022-03-18 18:21:17 +08:00
RISCVSubtarget.cpp
[RISCV] Support 'generic' as a valid CPU name.
2022-03-09 16:43:22 -08:00
RISCVSubtarget.h
[RISCV] Add +experimental-zvfh extension to cover half types in vectors.
2022-03-17 10:04:02 -07:00
RISCVSystemOperands.td
[RISCV] Initially support the K-extension instructions on the LLVM MC layer
2022-01-24 14:45:35 +08:00
RISCVTargetMachine.cpp
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
RISCVTargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[RISCV] Add basic cost model for vector casting
2022-03-22 14:17:08 +08:00
RISCVTargetTransformInfo.h
[RISCV] Add basic cost model for vector casting
2022-03-22 14:17:08 +08:00