862 lines
44 KiB
LLVM
862 lines
44 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
|
|
; RUN: llc -mcpu=gfx942 -amdgpu-mfma-vgpr-form < %s | FileCheck %s
|
|
|
|
target triple = "amdgcn-amd-amdhsa"
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 7, v0
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 1.0
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 2.0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 v[28:31], v0, s[0:1] offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 v[24:27], v0, s[0:1] offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 v[20:23], v0, s[0:1] offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 v[16:19], v0, s[0:1] offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 v[12:15], v0, s[0:1] offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 v[8:11], v0, s[0:1] offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a0, 1.0
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a1, 2.0
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[32:63], a0, a1, v[0:31]
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: v_mov_b32_e32 v2, v32
|
|
; CHECK-NEXT: v_mov_b32_e32 v3, v33
|
|
; CHECK-NEXT: v_mov_b32_e32 v4, v34
|
|
; CHECK-NEXT: v_mov_b32_e32 v5, v35
|
|
; CHECK-NEXT: v_mov_b32_e32 v6, v36
|
|
; CHECK-NEXT: v_mov_b32_e32 v7, v37
|
|
; CHECK-NEXT: v_mov_b32_e32 v8, v38
|
|
; CHECK-NEXT: v_mov_b32_e32 v9, v39
|
|
; CHECK-NEXT: v_mov_b32_e32 v10, v40
|
|
; CHECK-NEXT: v_mov_b32_e32 v11, v41
|
|
; CHECK-NEXT: v_mov_b32_e32 v12, v42
|
|
; CHECK-NEXT: v_mov_b32_e32 v13, v43
|
|
; CHECK-NEXT: v_mov_b32_e32 v14, v44
|
|
; CHECK-NEXT: v_mov_b32_e32 v15, v45
|
|
; CHECK-NEXT: v_mov_b32_e32 v16, v46
|
|
; CHECK-NEXT: v_mov_b32_e32 v17, v47
|
|
; CHECK-NEXT: v_mov_b32_e32 v18, v48
|
|
; CHECK-NEXT: v_mov_b32_e32 v19, v49
|
|
; CHECK-NEXT: v_mov_b32_e32 v20, v50
|
|
; CHECK-NEXT: v_mov_b32_e32 v21, v51
|
|
; CHECK-NEXT: v_mov_b32_e32 v22, v52
|
|
; CHECK-NEXT: v_mov_b32_e32 v23, v53
|
|
; CHECK-NEXT: v_mov_b32_e32 v24, v54
|
|
; CHECK-NEXT: v_mov_b32_e32 v25, v55
|
|
; CHECK-NEXT: v_mov_b32_e32 v26, v56
|
|
; CHECK-NEXT: v_mov_b32_e32 v27, v57
|
|
; CHECK-NEXT: v_mov_b32_e32 v28, v58
|
|
; CHECK-NEXT: v_mov_b32_e32 v29, v59
|
|
; CHECK-NEXT: v_mov_b32_e32 v30, v60
|
|
; CHECK-NEXT: v_mov_b32_e32 v31, v61
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], a0, a1, v[0:31]
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1]
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
|
|
%in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
|
|
%mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %in.1, i32 0, i32 0, i32 0)
|
|
%mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.1, i32 0, i32 0, i32 0)
|
|
%tmp.1 = shufflevector <32 x float> %mai.2, <32 x float> %mai.1, <32 x i32> <i32 32, i32 33, i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29>
|
|
%mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %tmp.1, i32 0, i32 0, i32 0)
|
|
store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_noshuffle(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_noshuffle:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 7, v0
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 1.0
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 2.0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 v[28:31], v0, s[0:1] offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 v[24:27], v0, s[0:1] offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 v[20:23], v0, s[0:1] offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 v[16:19], v0, s[0:1] offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 v[12:15], v0, s[0:1] offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 v[8:11], v0, s[0:1] offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 v[4:7], v0, s[0:1] offset:16
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: global_load_dwordx4 v[0:3], v0, s[0:1]
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 0
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1]
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
|
|
%in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
|
|
%mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %in.1, i32 0, i32 0, i32 0)
|
|
%mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.1, i32 0, i32 0, i32 0)
|
|
%mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.2, i32 0, i32 0, i32 0)
|
|
store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm0_src2(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm0_src2:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 1.0
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 2.0
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1]
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
|
|
%in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
|
|
%mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> zeroinitializer, i32 0, i32 0, i32 0)
|
|
%mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.1, i32 0, i32 0, i32 0)
|
|
%mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.2, i32 0, i32 0, i32 0)
|
|
store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm1_src2(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_mfma_f32_32x32x1f32_rewrite_vgpr_mfma_imm1_src2:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 1.0
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 2.0
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, 1.0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], v32, v33, v[0:31]
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1]
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
|
|
%in.1 = load <32 x float>, ptr addrspace(1) %gep, align 128
|
|
%mai.1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> splat (float 1.000000e+00), i32 0, i32 0, i32 0)
|
|
%mai.2 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.1, i32 0, i32 0, i32 0)
|
|
%mai.3 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 1.000000e+00, float 2.000000e+00, <32 x float> %mai.2, i32 0, i32 0, i32 0)
|
|
store <32 x float> %mai.3, ptr addrspace(1) %arg, align 128
|
|
ret void
|
|
}
|
|
|
|
; The inline asm requires the value be copied to an AGPR class, not
|
|
; the AV_* pseudo we usually expect for register allocator live range
|
|
; splits.
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_to_agpr_class(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_to_agpr_class:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 7, v0
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 2.0
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 4.0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 a[28:31], v0, s[0:1] offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 a[24:27], v0, s[0:1] offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 a[20:23], v0, s[0:1] offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 a[16:19], v0, s[0:1] offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 a[12:15], v0, s[0:1] offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 a[8:11], v0, s[0:1] offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 a[4:7], v0, s[0:1] offset:16
|
|
; CHECK-NEXT: global_load_dwordx4 a[0:3], v0, s[0:1]
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v32, v33, a[0:31]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_endpgm
|
|
bb:
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <32 x float>, ptr addrspace(1) %arg, i32 %id
|
|
%in = load <32 x float>, ptr addrspace(1) %gep, align 128
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 2.0, float 4.0, <32 x float> %in, i32 0, i32 0, i32 0)
|
|
call void asm sideeffect "; use $0", "a"(<32 x float> %mai)
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_imm_src2(float %arg0, float %arg1) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_imm_src2:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v0, v1, 2.0
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
bb:
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> splat (float 2.0), i32 0, i32 0, i32 0)
|
|
call void asm sideeffect "; use $0", "a"(<32 x float> %mai)
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_subreg_extract0(float %arg0, float %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_extract0:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 a[28:31], v[2:3], off offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 a[24:27], v[2:3], off offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 a[20:23], v[2:3], off offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 a[16:19], v[2:3], off offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 a[12:15], v[2:3], off offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 a[8:11], v[2:3], off offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 a[4:7], v[2:3], off offset:16
|
|
; CHECK-NEXT: global_load_dwordx4 a[0:3], v[2:3], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v0, v1, a[0:31]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:3]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
bb:
|
|
%src2 = load <32 x float>, ptr addrspace(1) %ptr
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%extract.sub4 = shufflevector <32 x float> %mai, <32 x float> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
call void asm sideeffect "; use $0", "a"(<4 x float> %extract.sub4)
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_subreg_extract1(float %arg0, float %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_extract1:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 a[28:31], v[2:3], off offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 a[24:27], v[2:3], off offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 a[20:23], v[2:3], off offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 a[16:19], v[2:3], off offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 a[12:15], v[2:3], off offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 a[8:11], v[2:3], off offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 a[4:7], v[2:3], off offset:16
|
|
; CHECK-NEXT: global_load_dwordx4 a[0:3], v[2:3], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v0, v1, a[0:31]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[4:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
bb:
|
|
%src2 = load <32 x float>, ptr addrspace(1) %ptr
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%extract.sub4 = shufflevector <32 x float> %mai, <32 x float> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
|
|
call void asm sideeffect "; use $0", "a"(<4 x float> %extract.sub4)
|
|
ret void
|
|
}
|
|
|
|
; odd offset
|
|
define void @test_rewrite_mfma_subreg_extract2(float %arg0, float %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_extract2:
|
|
; CHECK: ; %bb.0: ; %bb
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 a[28:31], v[2:3], off offset:112
|
|
; CHECK-NEXT: global_load_dwordx4 a[24:27], v[2:3], off offset:96
|
|
; CHECK-NEXT: global_load_dwordx4 a[20:23], v[2:3], off offset:80
|
|
; CHECK-NEXT: global_load_dwordx4 a[16:19], v[2:3], off offset:64
|
|
; CHECK-NEXT: global_load_dwordx4 a[12:15], v[2:3], off offset:48
|
|
; CHECK-NEXT: global_load_dwordx4 a[8:11], v[2:3], off offset:32
|
|
; CHECK-NEXT: global_load_dwordx4 a[4:7], v[2:3], off offset:16
|
|
; CHECK-NEXT: global_load_dwordx4 a[0:3], v[2:3], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v0, v1, a[0:31]
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a0, a1
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a1, a2
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a2, a3
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a3, a4
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:3]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
bb:
|
|
%src2 = load <32 x float>, ptr addrspace(1) %ptr
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float %arg0, float %arg1, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%extract.sub4 = shufflevector <32 x float> %mai, <32 x float> poison, <4 x i32> <i32 1, i32 2, i32 3, i32 4>
|
|
call void asm sideeffect "; use $0", "a"(<4 x float> %extract.sub4)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @illegal_mfma_after_rewrite() #1 {
|
|
; CHECK-LABEL: illegal_mfma_after_rewrite:
|
|
; CHECK: ; %bb.0: ; %entry
|
|
; CHECK-NEXT: s_mov_b32 s0, 0
|
|
; CHECK-NEXT: s_mov_b32 s1, s0
|
|
; CHECK-NEXT: v_mov_b64_e32 v[8:9], s[0:1]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def s[0:3]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mov_b64_e32 v[6:7], s[2:3]
|
|
; CHECK-NEXT: v_mov_b64_e32 v[4:5], s[0:1]
|
|
; CHECK-NEXT: s_mov_b32 s0, 0x3c003c00
|
|
; CHECK-NEXT: s_mov_b32 s1, s0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[8:9], v[8:9], v[4:7]
|
|
; CHECK-NEXT: v_mov_b64_e32 v[12:13], s[0:1]
|
|
; CHECK-NEXT: s_mov_b32 s0, 0x7e007e00
|
|
; CHECK-NEXT: s_mov_b32 s1, s0
|
|
; CHECK-NEXT: v_mov_b64_e32 v[10:11], s[0:1]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[14:17], v[8:9], v[12:13], v[4:7]
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a0, v0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[18:21], v[8:9], v[10:11], v[4:7]
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a1, v1
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a2, v2
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a3, v3
|
|
; CHECK-NEXT: v_mov_b32_e32 v4, 0x7fc00000
|
|
; CHECK-NEXT: v_mov_b32_e32 v5, v4
|
|
; CHECK-NEXT: v_mov_b32_e32 v6, v4
|
|
; CHECK-NEXT: v_mov_b32_e32 v7, v4
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[14:17], v[8:9], v[8:9], v[14:17]
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[22:25], v[8:9], v[8:9], v[4:7]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def v[4:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[8:9], v[12:13], v[4:7]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[26:29], v[8:9], v[8:9], v[4:7]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[8:9], v[8:9], v[0:3]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[22:25], v[8:9], v[8:9], v[22:25]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[4:7], v[8:9], v[8:9], v[26:29]
|
|
; CHECK-NEXT: s_nop 5
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v23, v14
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[14:17], v[8:9], v[8:9], v[18:21]
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[12:13], v[8:9], v[0:3]
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v19, a3
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v18, a2
|
|
; CHECK-NEXT: v_mov_b64_e32 v[20:21], 0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v17, a1
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v16, a0
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v15, v22
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v14, v14
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[16:19], v[8:9], v[8:9], v[16:19]
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v12, v0
|
|
; CHECK-NEXT: global_store_short v[20:21], v23, off
|
|
; CHECK-NEXT: buffer_wbl2 sc0 sc1
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: buffer_inv sc0 sc1
|
|
; CHECK-NEXT: v_mfma_f32_16x16x16_f16 v[0:3], v[10:11], v[8:9], v[4:7]
|
|
; CHECK-NEXT: global_store_short v[20:21], v15, off
|
|
; CHECK-NEXT: buffer_wbl2 sc0 sc1
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: buffer_inv sc0 sc1
|
|
; CHECK-NEXT: global_store_short v[20:21], v14, off
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v14, v16
|
|
; CHECK-NEXT: buffer_wbl2 sc0 sc1
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: buffer_inv sc0 sc1
|
|
; CHECK-NEXT: global_store_short v[20:21], v14, off
|
|
; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0
|
|
; CHECK-NEXT: buffer_wbl2 sc0 sc1
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: buffer_inv sc0 sc1
|
|
; CHECK-NEXT: global_store_short v[20:21], v12, off
|
|
; CHECK-NEXT: buffer_wbl2 sc0 sc1
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: buffer_inv sc0 sc1
|
|
; CHECK-NEXT: global_store_short v[20:21], v0, off
|
|
; CHECK-NEXT: s_endpgm
|
|
entry:
|
|
%k0 = call <4 x float> asm sideeffect "; def $0", "=s"()
|
|
%i2 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %k0, i32 0, i32 0, i32 0)
|
|
%i4 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> splat (half 0xH3C00), <4 x float> %k0, i32 0, i32 0, i32 0)
|
|
%i6 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> splat (half 0xH7E00), <4 x float> %k0, i32 0, i32 0, i32 0)
|
|
%i5 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> splat (float 0x7FF8000000000000), i32 0, i32 0, i32 0)
|
|
%k = call <4 x float> asm sideeffect "; def $0", "=v"()
|
|
%i1 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %k, i32 0, i32 0, i32 0)
|
|
%i7 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> splat (half 0xH3C00), <4 x float> %k, i32 0, i32 0, i32 0)
|
|
%i17 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i1, i32 0, i32 0, i32 0)
|
|
%i19 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i4, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.0 = extractelement <4 x float> %i19, i64 0
|
|
%conv.0 = fptrunc float %c_thread_buf.0 to half
|
|
store half %conv.0, ptr addrspace(1) null, align 2
|
|
fence seq_cst
|
|
%i22 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i5, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.1 = extractelement <4 x float> %i22, i64 0
|
|
%conv1 = fptrunc float %c_thread_buf.1 to half
|
|
store half %conv1, ptr addrspace(1) null, align 2
|
|
fence seq_cst
|
|
%i23 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i6, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.2 = extractelement <4 x float> %i23, i64 0
|
|
%conv2 = fptrunc float %c_thread_buf.2 to half
|
|
store half %conv2, ptr addrspace(1) null, align 2
|
|
fence seq_cst
|
|
%i25 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i2, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.3 = extractelement <4 x float> %i25, i64 0
|
|
%conv3 = fptrunc float %c_thread_buf.3 to half
|
|
store half %conv3, ptr addrspace(1) null, align 2
|
|
fence seq_cst
|
|
%i26 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i7, i32 0, i32 0, i32 0)
|
|
%i27 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> splat (half 0xH3C00), <4 x half> zeroinitializer, <4 x float> %i26, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.4 = extractelement <4 x float> %i27, i64 0
|
|
%conv4 = fptrunc float %c_thread_buf.4 to half
|
|
store half %conv4, ptr addrspace(1) null, align 2
|
|
fence seq_cst
|
|
%i31 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> splat (half 0xH7E00), <4 x half> zeroinitializer, <4 x float> %i17, i32 0, i32 0, i32 0)
|
|
%c_thread_buf.5 = extractelement <4 x float> %i31, i64 0
|
|
%conv5 = fptrunc float %c_thread_buf.5 to half
|
|
store half %conv5, ptr addrspace(1) null, align 2
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_subreg_insert0(float %arg0, float %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_insert0:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 a[0:3], v[2:3], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_4x4x1_16b_f32 a[0:3], v0, v1, a[0:3]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%src2 = load <4 x float>, ptr addrspace(1) %ptr
|
|
%mai = call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float %arg0, float %arg1, <4 x float> %src2, i32 0, i32 0, i32 0)
|
|
%insert.sub0 = shufflevector <4 x float> %mai, <4 x float> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
|
|
call void asm sideeffect "; use $0", "a"(<8 x float> %insert.sub0)
|
|
ret void
|
|
}
|
|
|
|
; odd offset
|
|
define void @test_rewrite_mfma_subreg_insert1(float %arg0, float %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_insert1:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx4 v[2:5], v[2:3], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f32_4x4x1_16b_f32 v[0:3], v0, v1, v[2:5]
|
|
; CHECK-NEXT: s_nop 3
|
|
; CHECK-NEXT: v_pk_mov_b32 v[0:1], v[0:1], v[2:3] op_sel:[1,0]
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a0, v0
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a1, v1
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a2, v3
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:7]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%src2 = load <4 x float>, ptr addrspace(1) %ptr
|
|
%mai = call <4 x float> @llvm.amdgcn.mfma.f32.4x4x1f32(float %arg0, float %arg1, <4 x float> %src2, i32 0, i32 0, i32 0)
|
|
%insert.sub0 = shufflevector <4 x float> %mai, <4 x float> poison, <8 x i32> <i32 1, i32 2, i32 3, i32 4, i32 poison, i32 poison, i32 poison, i32 poison>
|
|
call void asm sideeffect "; use $0", "a"(<8 x float> %insert.sub0)
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_subreg_insert2(double %arg0, double %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_subreg_insert2:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: global_load_dwordx2 a[0:1], v[4:5], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: v_mfma_f64_4x4x4_4b_f64 a[0:1], v[0:1], v[2:3], a[0:1]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:3]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%src2 = load double, ptr addrspace(1) %ptr
|
|
%mai = call double @llvm.amdgcn.mfma.f64.4x4x4f64(double %arg0, double %arg1, double %src2, i32 0, i32 0, i32 0)
|
|
%insert.sub0 = insertelement <2 x double> poison, double %mai, i32 0
|
|
call void asm sideeffect "; use $0", "a"(<2 x double> %insert.sub0)
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_from_agpr_class(ptr addrspace(1) %arg0, ptr addrspace(1) %arg1) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_from_agpr_class:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a32, v0
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v63, a31
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v62, a30
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v61, a29
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v60, a28
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v59, a27
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v58, a26
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v57, a25
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v56, a24
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v55, a23
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v54, a22
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v53, a21
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v52, a20
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v51, a19
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v50, a18
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v49, a17
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v48, a16
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v47, a15
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v46, a14
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v45, a13
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v44, a12
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v43, a11
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v42, a10
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v41, a9
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v40, a8
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v39, a7
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v38, a6
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v37, a5
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v36, a4
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v35, a3
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v34, a2
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v33, a1
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v32, a0
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a0, 2.0
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a1, 4.0
|
|
; CHECK-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 v[0:31], a0, a1, v[32:63]
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a0, v32
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a1, v33
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a2, v34
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a3, v35
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a4, v36
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a5, v37
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a6, v38
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a7, v39
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a8, v40
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a9, v41
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a10, v42
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a11, v43
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a12, v44
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a13, v45
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a14, v46
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a15, v47
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a16, v48
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a17, v49
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a18, v50
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a19, v51
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a20, v52
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a21, v53
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a22, v54
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a23, v55
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a24, v56
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a25, v57
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a26, v58
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a27, v59
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a28, v60
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a29, v61
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a30, v62
|
|
; CHECK-NEXT: v_accvgpr_write_b32 a31, v63
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 0x41000000
|
|
; CHECK-NEXT: v_mov_b32_e32 v34, 0x41800000
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v32, a32
|
|
; CHECK-NEXT: v_and_b32_e32 v32, 0x3ff, v32
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v33, v34, a[0:31]
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v32, 7, v32
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[0:1]
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v0, a0
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v24, a24
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v25, a25
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v26, a26
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v27, a27
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v1, a1
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v2, a2
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v3, a3
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v4, a4
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v5, a5
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v6, a6
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v7, a7
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v8, a8
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v9, a9
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v10, a10
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v11, a11
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v12, a12
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v13, a13
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v14, a14
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v15, a15
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v16, a16
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v17, a17
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v18, a18
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v19, a19
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v20, a20
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v21, a21
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v22, a22
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v23, a23
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v28, a28
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v29, a29
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v30, a30
|
|
; CHECK-NEXT: v_accvgpr_read_b32 v31, a31
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[24:27], s[2:3] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[28:31], s[2:3] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[16:19], s[2:3] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[20:23], s[2:3] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[8:11], s[2:3] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[12:15], s[2:3] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[0:3], s[2:3]
|
|
; CHECK-NEXT: global_store_dwordx4 v32, v[4:7], s[2:3] offset:16
|
|
; CHECK-NEXT: s_endpgm
|
|
%src2 = call <32 x float> asm sideeffect "; def $0", "=a"()
|
|
%mai0 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 2.0, float 4.0, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%mai1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 8.0, float 16.0, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <32 x float>, ptr addrspace(1) %arg0, i32 %id
|
|
store <32 x float> %mai0, ptr addrspace(1) %gep0, align 128
|
|
%gep1 = getelementptr <32 x float>, ptr addrspace(1) %arg1, i32 %id
|
|
store <32 x float> %mai1, ptr addrspace(1) %gep1, align 128
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_from_agpr_class_chain(ptr addrspace(1) %arg0) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_from_agpr_class_chain:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2.0
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_mov_b32_e32 v34, 4.0
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v1, v34, a[0:31]
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 0x41000000
|
|
; CHECK-NEXT: v_mov_b32_e32 v34, 0x41800000
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 7, v0
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v1, v34, a[0:31]
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[28:31], s[0:1] offset:112
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[24:27], s[0:1] offset:96
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[20:23], s[0:1] offset:80
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[16:19], s[0:1] offset:64
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[0:3], s[0:1]
|
|
; CHECK-NEXT: s_endpgm
|
|
%src2 = call <32 x float> asm sideeffect "; def $0", "=a"()
|
|
%mai0 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 2.0, float 4.0, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
%mai1 = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 8.0, float 16.0, <32 x float> %mai0, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr <32 x float>, ptr addrspace(1) %arg0, i32 %id
|
|
store <32 x float> %mai1, ptr addrspace(1) %gep0, align 128
|
|
ret void
|
|
}
|
|
|
|
; Untied case
|
|
define void @test_rewrite_mfma_copy_from_agpr_class_f64_4x4x4f64(double %arg0, double %arg1, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_copy_from_agpr_class_f64_4x4x4f64:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:1]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_and_b32_e32 v8, 0x3ff, v31
|
|
; CHECK-NEXT: v_mfma_f64_4x4x4_4b_f64 a[0:1], v[0:1], v[2:3], a[0:1]
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 3, v8
|
|
; CHECK-NEXT: v_mov_b32_e32 v3, 0
|
|
; CHECK-NEXT: v_lshl_add_u64 v[2:3], v[4:5], 0, v[2:3]
|
|
; CHECK-NEXT: s_nop 5
|
|
; CHECK-NEXT: global_store_dwordx2 v[2:3], a[0:1], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%src2 = call double asm sideeffect "; def $0", "=a"()
|
|
%mai = call double @llvm.amdgcn.mfma.f64.4x4x4f64(double %arg0, double %arg1, double %src2, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %ptr, i32 %id
|
|
store double %mai, ptr addrspace(1) %gep0, align 8
|
|
ret void
|
|
}
|
|
|
|
define void @test_rewrite_mfma_copy_from_agpr_class_f64_4x4x4f64_chain(double %arg0, double %arg1, double %arg2, double %arg3, ptr addrspace(1) %ptr) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_copy_from_agpr_class_f64_4x4x4f64_chain:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:1]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: v_mfma_f64_4x4x4_4b_f64 a[0:1], v[0:1], v[2:3], a[0:1]
|
|
; CHECK-NEXT: v_and_b32_e32 v2, 0x3ff, v31
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v2, 3, v2
|
|
; CHECK-NEXT: v_mov_b32_e32 v3, 0
|
|
; CHECK-NEXT: v_lshl_add_u64 v[2:3], v[8:9], 0, v[2:3]
|
|
; CHECK-NEXT: v_mfma_f64_4x4x4_4b_f64 a[0:1], v[4:5], v[6:7], a[0:1]
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: s_nop 0
|
|
; CHECK-NEXT: global_store_dwordx2 v[2:3], a[0:1], off
|
|
; CHECK-NEXT: s_waitcnt vmcnt(0)
|
|
; CHECK-NEXT: s_setpc_b64 s[30:31]
|
|
%src2 = call double asm sideeffect "; def $0", "=a"()
|
|
%mai0 = call double @llvm.amdgcn.mfma.f64.4x4x4f64(double %arg0, double %arg1, double %src2, i32 0, i32 0, i32 0)
|
|
%mai1 = call double @llvm.amdgcn.mfma.f64.4x4x4f64(double %arg2, double %arg3, double %mai0, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep0 = getelementptr double, ptr addrspace(1) %ptr, i32 %id
|
|
store double %mai1, ptr addrspace(1) %gep0, align 8
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_from_agpr_class_subreg(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_from_agpr_class_subreg:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2.0
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_mov_b32_e32 v18, 4.0
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x1_4b_f32 a[0:15], v1, v18, a[0:15]
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 6, v0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[12:15], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[8:11], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[4:7], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[0:3], s[0:1]
|
|
; CHECK-NEXT: s_endpgm
|
|
%def = call <32 x float> asm sideeffect "; def $0", "=a"()
|
|
%src2 = shufflevector <32 x float> %def, <32 x float> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
|
|
%mai = call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float 2.0, float 4.0, <16 x float> %src2, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <16 x float>, ptr addrspace(1) %arg, i32 %id
|
|
store <16 x float> %mai, ptr addrspace(1) %gep, align 64
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_from_agpr_class_subreg_odd(ptr addrspace(1) %arg) #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_from_agpr_class_subreg_odd:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: v_mov_b32_e32 v1, 2.0
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_mov_b32_e32 v18, 4.0
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a17, a16
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a16, a15
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a15, a14
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a14, a13
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a13, a12
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a12, a11
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a11, a10
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a10, a9
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a9, a8
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a8, a7
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a7, a6
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a6, a5
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a5, a4
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a4, a3
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a3, a2
|
|
; CHECK-NEXT: v_accvgpr_mov_b32 a2, a1
|
|
; CHECK-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0
|
|
; CHECK-NEXT: v_and_b32_e32 v0, 0x3ff, v0
|
|
; CHECK-NEXT: v_mfma_f32_16x16x1_4b_f32 a[2:17], v1, v18, a[2:17]
|
|
; CHECK-NEXT: v_lshlrev_b32_e32 v0, 6, v0
|
|
; CHECK-NEXT: s_waitcnt lgkmcnt(0)
|
|
; CHECK-NEXT: s_nop 7
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[14:17], s[0:1] offset:48
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[10:13], s[0:1] offset:32
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[6:9], s[0:1] offset:16
|
|
; CHECK-NEXT: global_store_dwordx4 v0, a[2:5], s[0:1]
|
|
; CHECK-NEXT: s_endpgm
|
|
%def = call <32 x float> asm sideeffect "; def $0", "=a"()
|
|
%src2 = shufflevector <32 x float> %def, <32 x float> poison, <16 x i32> <i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16>
|
|
%mai = call <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float 2.0, float 4.0, <16 x float> %src2, i32 0, i32 0, i32 0)
|
|
%id = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep = getelementptr <16 x float>, ptr addrspace(1) %arg, i32 %id
|
|
store <16 x float> %mai, ptr addrspace(1) %gep, align 64
|
|
ret void
|
|
}
|
|
|
|
; a->v->mfma->a
|
|
define amdgpu_kernel void @test_rewrite_mfma_direct_copy_from_agpr_class_copy_back() #0 {
|
|
; CHECK-LABEL: test_rewrite_mfma_direct_copy_from_agpr_class_copy_back:
|
|
; CHECK: ; %bb.0:
|
|
; CHECK-NEXT: v_mov_b32_e32 v32, 2.0
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; def a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: v_mov_b32_e32 v33, 4.0
|
|
; CHECK-NEXT: s_nop 1
|
|
; CHECK-NEXT: v_mfma_f32_32x32x1_2b_f32 a[0:31], v32, v33, a[0:31]
|
|
; CHECK-NEXT: ;;#ASMSTART
|
|
; CHECK-NEXT: ; use a[0:31]
|
|
; CHECK-NEXT: ;;#ASMEND
|
|
; CHECK-NEXT: s_endpgm
|
|
%src2 = call <32 x float> asm sideeffect "; def $0", "=a"()
|
|
%mai = call <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float 2.0, float 4.0, <32 x float> %src2, i32 0, i32 0, i32 0)
|
|
call void asm sideeffect "; use $0", "a"(<32 x float> %mai)
|
|
ret void
|
|
}
|
|
|
|
declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg) #2
|
|
declare <16 x float> @llvm.amdgcn.mfma.f32.16x16x1f32(float, float, <16 x float>, i32 immarg, i32 immarg, i32 immarg) #2
|
|
declare <32 x float> @llvm.amdgcn.mfma.f32.32x32x1f32(float, float, <32 x float>, i32 immarg, i32 immarg, i32 immarg) #2
|
|
declare noundef range(i32 0, 1024) i32 @llvm.amdgcn.workitem.id.x() #3
|
|
|
|
attributes #0 = { nounwind "amdgpu-flat-work-group-size"="1,256" "amdgpu-waves-per-eu"="4,4" }
|
|
attributes #1 = { mustprogress nofree norecurse nounwind willreturn "amdgpu-waves-per-eu"="8,8" }
|
|
attributes #2 = { convergent nocallback nofree nosync nounwind willreturn memory(none) }
|
|
attributes #3 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
|