llvm-project

bf16.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

blend-any-of-reduction-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

blocks-with-dead-instructions.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

dead-ops-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

defaults.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

divrem.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

evl-compatible-loops.ll

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evl-iv-simplify.ll

[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005 )

2025-05-14 13:49:50 -07:00

f16.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

first-order-recurrence-scalable-vf1.ll

[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772 )

2025-06-18 16:03:20 +08:00

fminimumnum.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

force-vect-msg.ll

[LoopVectorize][NFC] Disable output for tests that don't need it (#124747 )

2025-01-29 08:09:50 +00:00

illegal-type.ll

[VPlan] Don't access canonical IV in VPWidenPointerInduction::execute.

2025-03-15 21:32:48 +00:00

induction-costs.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

inloop-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

interleaved-accesses-zve32x.ll

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interleaved-accesses.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

interleaved-cost.ll

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interleaved-masked-access.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

lit.local.cfg

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lmul.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

low-trip-count.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

mask-index-type.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

masked_gather_scatter.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

only-compute-cost-for-vplan-vfs.ll

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ordered-reduction.ll

[VPlan] Remove no-op SCALAR-STEPS after unrolling. (#123655 )

2025-03-25 12:57:24 +00:00

partial-reduce-dot-product.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

pr88802.ll

[LV] Stengthen loop-invariance checks in isPredicatedInst (#140744 )

2025-06-20 14:01:48 +01:00

preserve-dbg-loc.ll

[VPlan] Set debug location for VPReduction/VPWidenIntrinsicRecipe. (#120054 )

2024-12-27 10:37:21 +08:00

reg-usage-bf16.ll

[LV] Fix MVE regression from #132190 (#141736 )

2025-06-16 09:58:03 +01:00

reg-usage-f16.ll

[LV] Fix MVE regression from #132190 (#141736 )

2025-06-16 09:58:03 +01:00

reg-usage.ll

[LV] Fix MVE regression from #132190 (#141736 )

2025-06-16 09:58:03 +01:00

remark-reductions.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

riscv-interleaved.ll

[LoopVectorize][NFC] Disable output for tests that don't need it (#124747 )

2025-01-29 08:09:50 +00:00

riscv-unroll.ll

[VPlan] Remove no-op SCALAR-STEPS after unrolling. (#123655 )

2025-03-25 12:57:24 +00:00

riscv-vector-reverse-output.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

riscv-vector-reverse.ll

[LV] Update test after 4ac4726d00.

2025-06-25 09:54:54 +01:00

safe-dep-distance.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

scalable-basics.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

scalable-reductions.ll

[RISCV] Enable scalable loop vectorization for fmax/fmin reductions with f16/bf16 type for zvfhmin/zvfbfmin (#129629 )

2025-03-04 16:49:24 +08:00

scalable-tailfold.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

scalable-vf-hint.ll

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select-cmp-reduction.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

select-invariant-cond-cost.ll

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short-trip-count.ll

[VPlan] Use InstSimplifyFolder instead of TargetFolder (#141222 )

2025-05-28 11:00:14 +02:00

strided-accesses.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

tail-folding-cost.ll

[LoopVectorize] Add cost of generating tail-folding mask to the loop (#130565 )

2025-03-21 09:24:56 +00:00

truncate-to-minimal-bitwidth-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

truncate-to-minimal-bitwidth-evl-crash.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

type-info-cache-evl-crash.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

uniform-load-store.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

unroll-in-loop-vectorizer.ll

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veclib-function-calls.ll

…

vectorize-force-tail-with-evl-bin-unary-ops-args.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-call-intrinsics.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-cast-intrinsics.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-cond-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-div.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-fixed-order-recurrence.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-gather-scatter.ll

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vectorize-force-tail-with-evl-inloop-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-interleave.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-intermediate-store.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-iv32.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-known-no-overflow.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-masked-loadstore.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-no-masking.ll

…

vectorize-force-tail-with-evl-ordered-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-reduction-cost.ll

[LoopVectorize][NFC] Disable output for tests that don't need it (#124747 )

2025-01-29 08:09:50 +00:00

vectorize-force-tail-with-evl-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-reverse-load-store.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-safe-dep-distance.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532 )

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-uniform-store.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vectorize-vp-intrinsics.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963 )

2025-06-20 11:37:27 -07:00

vf-will-not-generate-any-vector-insts.ll

[VPlan] Add incoming values for all predecessor to ResumePHI (NFCI).

2025-02-09 11:20:20 +00:00

vplan-vp-call-intrinsics.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

vplan-vp-cast-intrinsics.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

vplan-vp-intrinsics-fixed-order-recurrence.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

vplan-vp-intrinsics-reduction.ll

[LV] Replace redundant ExtractLastElement of reduction result (NFC).

2025-06-24 21:48:58 +01:00

vplan-vp-intrinsics.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

vplan-vp-select-intrinsics.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

zvl32b.ll

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