55aff64d2c
The patch add 16 bytes load size for function PPCTTIImpl::enableMemCmpExpansion and fold i128 equality/inequality compares of two loads into a vectorized compare using vcmpequb.p when Altivec is available. Rationale: A scalar i128 SETCC (eq/ne) normally lowers to multiple scalar ops. On VSX-capable subtargets, we can instead reinterpret the i128 loads as v16i8 vectors and use the Altive vcmpequb.p instruction to perform a full 128-bit equality check in a single vector compare. Example Result: This transformation replaces memcmp(a, b, 16) with two vector loads and one vector compare instruction.
142 lines
6.4 KiB
LLVM
142 lines
6.4 KiB
LLVM
; RUN: llc -o - -mtriple=powerpc64le-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s
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; RUN: llc -o - -mtriple=powerpc64-unknown-gnu-linux -stop-after codegenprepare %s | FileCheck %s --check-prefix=CHECK-BE
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define signext i32 @test1(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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entry:
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; CHECK-LABEL: @test1(
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; CHECK: [[LOAD0:%[0-9]+]] = load i128, ptr %buffer1, align 1
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; CHECK-NEXT: [[LOAD1:%[0-9]+]] = load i128, ptr %buffer2, align 1
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; CHECK-NEXT: [[CALL1:%[0-9]+]] = call i128 @llvm.bswap.i128(i128 [[LOAD0]])
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; CHECK-NEXT: [[CALL2:%[0-9]+]] = call i128 @llvm.bswap.i128(i128 [[LOAD1]])
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; CHECK-NEXT: [[CALL3:%[0-9]+]] = call i32 @llvm.ucmp.i32.i128(i128 [[CALL1]], i128 [[CALL2]])
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; CHECK-NEXT: ret i32 [[CALL3]]
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; CHECK-BE-LABEL: @test1(
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; CHECK-BE: [[LOAD0:%[0-9]+]] = load i128, ptr %buffer1, align 1
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; CHECK-BE-NEXT: [[LOAD1:%[0-9]+]] = load i128, ptr %buffer2, align 1
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; CHECK-BE-NEXT: [[CALL0:%[0-9]+]] = call i32 @llvm.ucmp.i32.i128(i128 [[LOAD0]], i128 [[LOAD1]])
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; CHECK-BE-NEXT: ret i32 [[CALL0]]
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 16)
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ret i32 %call
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}
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declare signext i32 @memcmp(ptr nocapture, ptr nocapture, i64) local_unnamed_addr #1
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define signext i32 @test2(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: @test2(
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; CHECK: [[LOAD1:%[0-9]+]] = load i32, ptr
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; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
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; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
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; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
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; CHECK-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[BSWAP1]], i32 [[BSWAP2]])
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; CHECK-NEXT: ret i32 [[UCMP]]
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; CHECK-BE-LABEL: @test2(
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; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, ptr
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; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
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; CHECK-BE-NEXT: [[UCMP:%[0-9]+]] = call i32 @llvm.ucmp.i32.i32(i32 [[LOAD1]], i32 [[LOAD2]])
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; CHECK-BE-NEXT: ret i32 [[UCMP]]
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entry:
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 4)
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ret i32 %call
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}
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define signext i32 @test3(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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; CHECK-LABEL: res_block:{{.*}}
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; CHECK: [[ICMP2:%[0-9]+]] = icmp ult i64
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; CHECK-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
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; CHECK-NEXT: br label %endblock
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; CHECK-LABEL: loadbb:{{.*}}
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; CHECK: [[LOAD1:%[0-9]+]] = load i64, ptr
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; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
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; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD1]])
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; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i64 @llvm.bswap.i64(i64 [[LOAD2]])
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; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[BSWAP1]], [[BSWAP2]]
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; CHECK-NEXT: br i1 [[ICMP]], label %loadbb1, label %res_block
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; CHECK-LABEL: loadbb1:{{.*}}
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; CHECK: [[LOAD1:%[0-9]+]] = load i32, ptr
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; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
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; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD1]])
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; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i32 @llvm.bswap.i32(i32 [[LOAD2]])
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[BSWAP1]] to i64
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[BSWAP2]] to i64
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; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
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; CHECK-NEXT: br i1 [[ICMP]], label %loadbb2, label %res_block
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; CHECK-LABEL: loadbb2:{{.*}}
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; CHECK: [[LOAD1:%[0-9]+]] = load i16, ptr
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; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i16, ptr
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; CHECK-NEXT: [[BSWAP1:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD1]])
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; CHECK-NEXT: [[BSWAP2:%[0-9]+]] = call i16 @llvm.bswap.i16(i16 [[LOAD2]])
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[BSWAP1]] to i64
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[BSWAP2]] to i64
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; CHECK-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
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; CHECK-NEXT: br i1 [[ICMP]], label %loadbb3, label %res_block
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; CHECK-LABEL: loadbb3:{{.*}}
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; CHECK: [[LOAD1:%[0-9]+]] = load i8, ptr
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; CHECK-NEXT: [[LOAD2:%[0-9]+]] = load i8, ptr
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; CHECK-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
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; CHECK-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
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; CHECK-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
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; CHECK-NEXT: br label %endblock
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; CHECK-BE-LABEL: res_block:{{.*}}
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; CHECK-BE: [[ICMP2:%[0-9]+]] = icmp ult i64
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; CHECK-BE-NEXT: [[SELECT:%[0-9]+]] = select i1 [[ICMP2]], i32 -1, i32 1
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; CHECK-BE-NEXT: br label %endblock
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; CHECK-BE-LABEL: loadbb:{{.*}}
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; CHECK-BE: [[LOAD1:%[0-9]+]] = load i64, ptr
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; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i64, ptr
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; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[LOAD1]], [[LOAD2]]
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; CHECK-BE-NEXT: br i1 [[ICMP]], label %loadbb1, label %res_block
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; CHECK-BE: [[LOAD1:%[0-9]+]] = load i32, ptr
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; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i32, ptr
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; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i32 [[LOAD1]] to i64
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; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i32 [[LOAD2]] to i64
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; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
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; CHECK-BE-NEXT: br i1 [[ICMP]], label %loadbb2, label %res_block
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; CHECK-BE: [[LOAD1:%[0-9]+]] = load i16, ptr
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; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i16, ptr
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; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i16 [[LOAD1]] to i64
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; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i16 [[LOAD2]] to i64
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; CHECK-BE-NEXT: [[ICMP:%[0-9]+]] = icmp eq i64 [[ZEXT1]], [[ZEXT2]]
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; CHECK-BE-NEXT: br i1 [[ICMP]], label %loadbb3, label %res_block
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; CHECK-BE: [[LOAD1:%[0-9]+]] = load i8, ptr
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; CHECK-BE-NEXT: [[LOAD2:%[0-9]+]] = load i8, ptr
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; CHECK-BE-NEXT: [[ZEXT1:%[0-9]+]] = zext i8 [[LOAD1]] to i32
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; CHECK-BE-NEXT: [[ZEXT2:%[0-9]+]] = zext i8 [[LOAD2]] to i32
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; CHECK-BE-NEXT: [[SUB:%[0-9]+]] = sub i32 [[ZEXT1]], [[ZEXT2]]
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; CHECK-BE-NEXT: br label %endblock
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entry:
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 15)
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ret i32 %call
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}
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; CHECK: call = tail call signext i32 @memcmp
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; CHECK-BE: call = tail call signext i32 @memcmp
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define signext i32 @test4(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2) {
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entry:
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 129)
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ret i32 %call
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}
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define signext i32 @test5(ptr nocapture readonly %buffer1, ptr nocapture readonly %buffer2, i32 signext %SIZE) {
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; CHECK: call = tail call signext i32 @memcmp
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; CHECK-BE: call = tail call signext i32 @memcmp
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entry:
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%conv = sext i32 %SIZE to i64
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%call = tail call signext i32 @memcmp(ptr %buffer1, ptr %buffer2, i64 %conv)
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ret i32 %call
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}
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