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llvm-project/llvm/unittests/TargetParser
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Jim Lin 22707fd4a5
[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)
The spec can be found at:

https://github.com/andestech/andes-v5-isa/releases/tag/ast-v5_4_0-release.

The extension includes only two instructions: one for converting from
f32 to f16, and another for converting from f16 to f32.

This patch only implements MC support for XAndesBFHCvt.
2025-07-15 08:59:00 +08:00
..
CMakeLists.txt
…
CSKYTargetParserTest.cpp
[llvm] Use llvm::erase_if (NFC) (#141185)
2025-05-23 10:32:58 -07:00
Host.cpp
[AArch64] Add support for -mcpu=gb10. (#146515)
2025-07-07 11:14:26 +01:00
RISCVISAInfoTest.cpp
[RISCV] Add Andes XAndesBFHCvt (Andes Scalar BFLOAT16) extension (#148563)
2025-07-15 08:59:00 +08:00
RISCVTargetParserTest.cpp
[RISCV] Move the RISCVII namespaced enums into RISCVVType namespace in RISCVTargetParser.h. NFC (#127585)
2025-02-18 08:27:25 -08:00
TargetParserTest.cpp
[LLVM][AArch64] Relax SVE codegen predicates for sm4 instructions (#147524)
2025-07-08 17:04:21 +01:00
TripleTest.cpp
AArch64: Base MCAsmInfo type on binary format before OS (#147875)
2025-07-10 13:06:14 +09:00
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