Jeffrey Byrnes 5da7179cb3 [AMDGPU] Reland: Add IR LiveReg type-based optimization

2024-07-03 09:26:19 -07:00

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AArch64

[SDAG] Intersect poison-generating flags after CSE (#97434)

2024-07-03 20:32:46 +08:00

AMDGPU

[AMDGPU] Reland: Add IR LiveReg type-based optimization

2024-07-03 09:26:19 -07:00

ARC

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ARM

[SimplifyCFG] Simplify nested branches (#97067)

2024-07-01 03:35:39 +08:00

AVR

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BPF

[CodeGen] Use temp symbol for MBBs (#95031)

2024-06-20 13:18:41 +02:00

CSKY

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DirectX

[DirectX] Add stub PSV0 section (#96712)

2024-06-26 11:15:34 -07:00

Generic

Revert "[CodeGen][NewPM] Port machine-branch-prob to new pass manager" (#96858)

2024-06-27 15:00:17 +08:00

Hexagon

[llvm][CodeGen] Update checking method of loop-carried phi in window scheduler (#96288)

2024-06-26 09:56:09 +08:00

Inputs

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Lanai

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LoongArch

[LoongArch] Ensure PseudoLA* can be hoisted (#94723)

2024-06-25 18:53:17 +08:00

M68k

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Mips

Revert "Intrinsic: introduce minimumnum and maximumnum (#93841)"

2024-06-21 08:34:04 +02:00

MIR

[LLVM][MIR] Support parsing bfloat immediates in MIR parser (#96010)

2024-06-25 16:44:14 -04:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Support inline asm with 128-bit operand in NVPTX backend (#97113)

2024-07-01 16:30:33 -07:00

PowerPC

DAG: Call SimplifyDemandedBits on fcopysign sign value (#97151)

2024-07-01 12:19:17 +02:00

RISCV

[RISCV] Implement Intrinsics Support for XCValu Extension in CV32E40P (#85603)

2024-07-04 01:25:10 +10:00

SPARC

[NFC][SPARC] Fix typos and style mismatches

2024-06-19 21:44:48 +07:00

SPIRV

[SPIR-V] Improve type inference for a known instruction's builtin: OpGroupAsyncCopy (#96895)

2024-07-03 17:56:41 +02:00

SystemZ

[SystemZ] Address issue with supper large stack frames (#96318)

2024-06-27 09:23:35 -04:00

Thumb

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Thumb2

[ARM] Add tan intrinsic lowering (#95439)

2024-06-14 10:35:50 -04:00

VE

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WebAssembly

[WebAssembly] Update generic and bleeding-edge CPUs (#96584)

2024-07-01 19:12:01 -07:00

WinCFGuard

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WinEH

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X86

[X86] Add checkSignTestSetCCCombine - if X86ISD::CMP/OR is testing for signbits, attempt to test for the signbit source instead. (#97433)

2024-07-03 11:47:48 +01:00

XCore

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Xtensa

[Xtensa] Lower GlobalAddress/BlockAddress/JumpTable (#95256)

2024-06-25 12:21:33 +02:00