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llvm-project/llvm/test/CodeGen
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Christudasan Devadasan 5ebe91fcb2 [AMDGPU] Correctly set IsKill flag for VGPR spills in the prolog 
We always assume the vector register is dead or killed while
inserting the VGPR spills in the prolog. It is not always
true. Used the entry block liveIn data while setting the flag.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D124194
2022-12-17 11:48:44 +05:30
..
AArch64
Reland "[SimplifyCFG] FoldBranchToCommonDest(): deal with mismatched IV's in PHI's in common successor block"
2022-12-17 05:18:54 +03:00
AMDGPU
[AMDGPU] Correctly set IsKill flag for VGPR spills in the prolog
2022-12-17 11:48:44 +05:30
ARC
[ARC] Regenerate ldst.ll
2022-10-29 14:09:58 +01:00
ARM
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
AVR
[AVR] Do not use R0/R1 on avrtiny
2022-11-28 18:05:55 +01:00
BPF
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
CSKY
[CSKY][NFC] Fix check-all error due to change of expected output
2022-12-12 11:30:52 +08:00
DirectX
[NFC][DX] Update test case to use new opt flags
2022-12-09 13:16:49 -06:00
Generic
[NFC] Port codegen Generic tests that invoke opt to -passes= syntax
2022-12-09 01:04:47 +03:00
Hexagon
[Hexagon] Handle rounding beyond low 32 bits
2022-12-14 10:25:34 -08:00
Inputs
…
Lanai
…
LoongArch
[LoongArch] Add tests showing the optimization pipeline
2022-12-16 18:09:50 +08:00
M68k
Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."
2022-12-05 12:53:50 -06:00
Mips
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
MIR
AMDGPU: Remove ImagePSV and move images to addrspace 7
2022-11-30 11:32:34 +01:00
MLRegalloc
[mlgo] Use have_tflite instead of have_tf_api
2022-12-15 13:54:25 -08:00
MSP430
…
NVPTX
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
PowerPC
Reland "[SimplifyCFG] FoldBranchToCommonDest(): deal with mismatched IV's in PHI's in common successor block"
2022-12-17 05:18:54 +03:00
RISCV
[RISCV][VP] support vp.reduce.mul by ExpandVectorPredication
2022-12-17 10:49:47 +08:00
SPARC
[SPARC] Mark the %g0 register as constant & use it to materialize zeros
2022-12-13 17:25:42 -05:00
SPIRV
[SPIRV] support the enqueue_kernel builtin function
2022-11-01 02:52:08 +03:00
SystemZ
[NFC] Port codegen SystemZ tests that invoke opt to -passes= syntax
2022-12-09 01:04:47 +03:00
Thumb
[NFC] Port codegen Thumb tests that invoke opt to -passes= syntax
2022-12-09 01:04:47 +03:00
Thumb2
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
VE
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
WebAssembly
Revert "[SelectionDAG] Do not second-guess alignment for alloca"
2022-12-15 10:55:18 -06:00
WinCFGuard
…
WinEH
[NFC] Port one more codegen WinEH test to -passes= syntax
2022-12-09 02:07:27 +03:00
X86
Reland "[SimplifyCFG] FoldBranchToCommonDest(): deal with mismatched IV's in PHI's in common successor block"
2022-12-17 05:18:54 +03:00
XCore
Reapply "[CodeGen] Add new pass for late cleanup of redundant definitions."
2022-12-05 12:53:50 -06:00