Matt Arsenault 5f802be4e5 GlobalISel: Don't fail translate on intrinsics with metadata

2020-07-27 19:00:25 -04:00

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AArch64

[llvm][CodeGen] Addressing modes for SVE ldN.

2020-07-27 22:18:28 +00:00

AMDGPU

GlobalISel: Don't fail translate on intrinsics with metadata

2020-07-27 19:00:25 -04:00

ARC

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ARM

[Thumb] set code alignment for 16-bit load from constant pool

2020-07-22 10:12:41 +01:00

AVR

[AVR] Rewrite the function calling convention.

2020-06-23 21:36:18 +12:00

BPF

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

Generic

[llc] (almost) remove --print-machineinstrs

2020-07-20 10:43:28 -07:00

Hexagon

[llc] (almost) remove --print-machineinstrs

2020-07-20 10:43:28 -07:00

Inputs

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Lanai

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Mips

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

MIR

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

MSP430

[MSP430] Declare comparison LibCalls as returning i16 instead of i32

2020-06-30 11:04:22 +03:00

NVPTX

[NVPTX] Fix for NVPTX module asm regression

2020-06-24 11:17:09 -07:00

PowerPC

Revert "[PowerPC] Remove QPX/A2Q BGQ/BGP CNK support"

2020-07-27 21:07:00 +00:00

RISCV

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SPARC

[llvm-readobj] Update tests because of changes in llvm-readobj behavior

2020-07-20 10:39:04 +01:00

SystemZ

[SystemZ] Ensure -mno-vx disables any use of vector features

2020-07-23 15:34:59 +02:00

Thumb

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Thumb2

Rename t2-reduce-size -> thumb2-reduce-size

2020-07-27 13:42:13 -07:00

VE

[VE] Support symbol with offset value

2020-07-01 23:55:27 +09:00

WebAssembly

[WebAssembly] Fix store_unfolded_offset tests in simd-offset.ll

2020-07-23 16:05:20 -07:00

WinCFGuard

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WinEH

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X86

[X86][SSE] Relax 128-bit restriction on extract_subvector(ext_vector_inreg(X),0) -> ext_vector_inreg(extract_subvector(X,0)) fold

2020-07-27 17:50:36 +01:00

XCore

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