9dc3255cb9
This switches clang to use the data layouts from TargetParser, instead of maintaining its own copy of data layouts, which are required to match the backend data layouts. For now I've kept explicit calls to resetDataLayout(), just with the argument implied by the triple and ABI. Ideally this would happen automatically, but the way these classes are initialized currently doesn't offer a great place to do this. Previously resetDataLayout() also set the UserLabelPrefix. I've separated this out, with a reasonable default so that most targets don't need to worry about it. I've kept the explicit data layouts for TCE and SPIR (without the V). These seem to not correspond to real LLVM targets. I've also fixed the XCore data layout in TargetParser, which was incorrectly set to the same one as Xtensa. It was previously unused.
82 lines
2.5 KiB
C++
82 lines
2.5 KiB
C++
//===--- XCore.h - Declare XCore target feature support ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares XCore TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H
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#define LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H
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#include "clang/Basic/TargetInfo.h"
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#include "clang/Basic/TargetOptions.h"
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#include "llvm/Support/Compiler.h"
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#include "llvm/TargetParser/Triple.h"
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namespace clang {
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namespace targets {
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class LLVM_LIBRARY_VISIBILITY XCoreTargetInfo : public TargetInfo {
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public:
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XCoreTargetInfo(const llvm::Triple &Triple, const TargetOptions &)
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: TargetInfo(Triple) {
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NoAsmVariants = true;
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LongLongAlign = 32;
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SuitableAlign = 32;
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DoubleAlign = LongDoubleAlign = 32;
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SizeType = UnsignedInt;
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PtrDiffType = SignedInt;
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IntPtrType = SignedInt;
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WCharType = UnsignedChar;
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WIntType = UnsignedInt;
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UseZeroLengthBitfieldAlignment = true;
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resetDataLayout();
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}
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void getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const override;
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llvm::SmallVector<Builtin::InfosShard> getTargetBuiltins() const override;
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BuiltinVaListKind getBuiltinVaListKind() const override {
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return TargetInfo::VoidPtrBuiltinVaList;
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}
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std::string_view getClobbers() const override { return ""; }
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ArrayRef<const char *> getGCCRegNames() const override {
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static const char *const GCCRegNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr"
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};
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return llvm::ArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::GCCRegAlias> getGCCRegAliases() const override {
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return {};
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}
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bool validateAsmConstraint(const char *&Name,
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TargetInfo::ConstraintInfo &Info) const override {
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return false;
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}
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int getEHDataRegisterNumber(unsigned RegNo) const override {
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// R0=ExceptionPointerRegister R1=ExceptionSelectorRegister
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return (RegNo < 2) ? RegNo : -1;
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}
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bool allowsLargerPreferedTypeAlignment() const override { return false; }
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bool hasBitIntType() const override { return true; }
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};
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} // namespace targets
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} // namespace clang
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#endif // LLVM_CLANG_LIB_BASIC_TARGETS_XCORE_H
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