3e16aef2a6
Pass and return `long double`s indirectly, as specified in the psABI. This continues the patch at https://reviews.llvm.org/D89130. This should fix the issue at https://github.com/llvm/llvm-project/issues/41838.
423 lines
14 KiB
C++
423 lines
14 KiB
C++
//===- Sparc.cpp ----------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "ABIInfoImpl.h"
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#include "TargetInfo.h"
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#include <algorithm>
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using namespace clang;
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using namespace clang::CodeGen;
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//===----------------------------------------------------------------------===//
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// SPARC v8 ABI Implementation.
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// Based on the SPARC Compliance Definition version 2.4.1.
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//
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// Ensures that complex values are passed in registers.
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//
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namespace {
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class SparcV8ABIInfo : public DefaultABIInfo {
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public:
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SparcV8ABIInfo(CodeGenTypes &CGT) : DefaultABIInfo(CGT) {}
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private:
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ABIArgInfo classifyReturnType(QualType RetTy) const;
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ABIArgInfo classifyArgumentType(QualType Ty) const;
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void computeInfo(CGFunctionInfo &FI) const override;
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};
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} // end anonymous namespace
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ABIArgInfo SparcV8ABIInfo::classifyReturnType(QualType Ty) const {
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const auto *CT = Ty->getAs<ComplexType>();
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const auto *BT = Ty->getAs<BuiltinType>();
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if (CT)
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BT = CT->getElementType()->getAs<BuiltinType>();
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bool IsLongDouble = BT && BT->getKind() == BuiltinType::LongDouble;
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// long double _Complex is special in that it should be marked as inreg.
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if (CT)
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return IsLongDouble ? ABIArgInfo::getDirectInReg()
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: ABIArgInfo::getDirect();
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if (IsLongDouble)
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return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),
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/*ByVal=*/false);
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return DefaultABIInfo::classifyReturnType(Ty);
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}
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ABIArgInfo SparcV8ABIInfo::classifyArgumentType(QualType Ty) const {
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if (const auto *BT = Ty->getAs<BuiltinType>();
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BT && BT->getKind() == BuiltinType::LongDouble)
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return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace());
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return DefaultABIInfo::classifyArgumentType(Ty);
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}
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void SparcV8ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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FI.getReturnInfo() = classifyReturnType(FI.getReturnType());
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for (auto &Arg : FI.arguments())
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Arg.info = classifyArgumentType(Arg.type);
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}
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namespace {
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class SparcV8TargetCodeGenInfo : public TargetCodeGenInfo {
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public:
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SparcV8TargetCodeGenInfo(CodeGenTypes &CGT)
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: TargetCodeGenInfo(std::make_unique<SparcV8ABIInfo>(CGT)) {}
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llvm::Value *decodeReturnAddress(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override {
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int Offset;
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if (isAggregateTypeForABI(CGF.CurFnInfo->getReturnType()))
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Offset = 12;
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else
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Offset = 8;
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return CGF.Builder.CreateGEP(CGF.Int8Ty, Address,
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llvm::ConstantInt::get(CGF.Int32Ty, Offset));
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}
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llvm::Value *encodeReturnAddress(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override {
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int Offset;
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if (isAggregateTypeForABI(CGF.CurFnInfo->getReturnType()))
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Offset = -12;
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else
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Offset = -8;
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return CGF.Builder.CreateGEP(CGF.Int8Ty, Address,
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llvm::ConstantInt::get(CGF.Int32Ty, Offset));
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}
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};
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} // end anonymous namespace
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//===----------------------------------------------------------------------===//
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// SPARC v9 ABI Implementation.
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// Based on the SPARC Compliance Definition version 2.4.1.
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//
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// Function arguments a mapped to a nominal "parameter array" and promoted to
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// registers depending on their type. Each argument occupies 8 or 16 bytes in
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// the array, structs larger than 16 bytes are passed indirectly.
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//
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// One case requires special care:
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//
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// struct mixed {
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// int i;
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// float f;
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// };
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//
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// When a struct mixed is passed by value, it only occupies 8 bytes in the
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// parameter array, but the int is passed in an integer register, and the float
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// is passed in a floating point register. This is represented as two arguments
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// with the LLVM IR inreg attribute:
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//
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// declare void f(i32 inreg %i, float inreg %f)
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//
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// The code generator will only allocate 4 bytes from the parameter array for
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// the inreg arguments. All other arguments are allocated a multiple of 8
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// bytes.
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//
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namespace {
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class SparcV9ABIInfo : public ABIInfo {
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public:
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SparcV9ABIInfo(CodeGenTypes &CGT) : ABIInfo(CGT) {}
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private:
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ABIArgInfo classifyType(QualType RetTy, unsigned SizeLimit,
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unsigned &RegOffset) const;
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void computeInfo(CGFunctionInfo &FI) const override;
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RValue EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, QualType Ty,
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AggValueSlot Slot) const override;
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// Coercion type builder for structs passed in registers. The coercion type
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// serves two purposes:
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//
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// 1. Pad structs to a multiple of 64 bits, so they are passed 'left-aligned'
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// in registers.
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// 2. Expose aligned floating point elements as first-level elements, so the
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// code generator knows to pass them in floating point registers.
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//
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// We also compute the InReg flag which indicates that the struct contains
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// aligned 32-bit floats.
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//
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struct CoerceBuilder {
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llvm::LLVMContext &Context;
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const llvm::DataLayout &DL;
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SmallVector<llvm::Type*, 8> Elems;
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uint64_t Size;
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bool InReg;
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CoerceBuilder(llvm::LLVMContext &c, const llvm::DataLayout &dl)
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: Context(c), DL(dl), Size(0), InReg(false) {}
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// Pad Elems with integers until Size is ToSize.
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void pad(uint64_t ToSize) {
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assert(ToSize >= Size && "Cannot remove elements");
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if (ToSize == Size)
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return;
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// Finish the current 64-bit word.
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uint64_t Aligned = llvm::alignTo(Size, 64);
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if (Aligned > Size && Aligned <= ToSize) {
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Elems.push_back(llvm::IntegerType::get(Context, Aligned - Size));
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Size = Aligned;
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}
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// Add whole 64-bit words.
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while (Size + 64 <= ToSize) {
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Elems.push_back(llvm::Type::getInt64Ty(Context));
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Size += 64;
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}
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// Final in-word padding.
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if (Size < ToSize) {
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Elems.push_back(llvm::IntegerType::get(Context, ToSize - Size));
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Size = ToSize;
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}
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}
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// Add a floating point element at Offset.
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void addFloat(uint64_t Offset, llvm::Type *Ty, unsigned Bits) {
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// Unaligned floats are treated as integers.
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if (Offset % Bits)
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return;
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// The InReg flag is only required if there are any floats < 64 bits.
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if (Bits < 64)
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InReg = true;
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pad(Offset);
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Elems.push_back(Ty);
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Size = Offset + Bits;
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}
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// Add a struct type to the coercion type, starting at Offset (in bits).
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void addStruct(uint64_t Offset, llvm::StructType *StrTy) {
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const llvm::StructLayout *Layout = DL.getStructLayout(StrTy);
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for (unsigned i = 0, e = StrTy->getNumElements(); i != e; ++i) {
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llvm::Type *ElemTy = StrTy->getElementType(i);
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uint64_t ElemOffset = Offset + Layout->getElementOffsetInBits(i);
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switch (ElemTy->getTypeID()) {
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case llvm::Type::StructTyID:
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addStruct(ElemOffset, cast<llvm::StructType>(ElemTy));
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break;
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case llvm::Type::FloatTyID:
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addFloat(ElemOffset, ElemTy, 32);
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break;
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case llvm::Type::DoubleTyID:
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addFloat(ElemOffset, ElemTy, 64);
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break;
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case llvm::Type::FP128TyID:
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addFloat(ElemOffset, ElemTy, 128);
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break;
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case llvm::Type::PointerTyID:
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if (ElemOffset % 64 == 0) {
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pad(ElemOffset);
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Elems.push_back(ElemTy);
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Size += 64;
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}
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break;
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default:
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break;
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}
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}
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}
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// Check if Ty is a usable substitute for the coercion type.
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bool isUsableType(llvm::StructType *Ty) const {
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return llvm::ArrayRef(Elems) == Ty->elements();
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}
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// Get the coercion type as a literal struct type.
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llvm::Type *getType() const {
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if (Elems.size() == 1)
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return Elems.front();
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else
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return llvm::StructType::get(Context, Elems);
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}
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};
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};
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} // end anonymous namespace
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ABIArgInfo SparcV9ABIInfo::classifyType(QualType Ty, unsigned SizeLimit,
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unsigned &RegOffset) const {
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if (Ty->isVoidType())
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return ABIArgInfo::getIgnore();
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auto &Context = getContext();
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auto &VMContext = getVMContext();
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uint64_t Size = Context.getTypeSize(Ty);
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unsigned Alignment = Context.getTypeAlign(Ty);
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bool NeedPadding = (Alignment > 64) && (RegOffset % 2 != 0);
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// Anything too big to fit in registers is passed with an explicit indirect
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// pointer / sret pointer.
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if (Size > SizeLimit) {
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RegOffset += 1;
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return getNaturalAlignIndirect(
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Ty, /*AddrSpace=*/getDataLayout().getAllocaAddrSpace(),
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/*ByVal=*/false);
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}
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// Treat an enum type as its underlying type.
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if (const auto *ED = Ty->getAsEnumDecl())
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Ty = ED->getIntegerType();
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// Integer types smaller than a register are extended.
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if (Size < 64 && Ty->isIntegerType()) {
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RegOffset += 1;
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return ABIArgInfo::getExtend(Ty);
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}
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if (const auto *EIT = Ty->getAs<BitIntType>())
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if (EIT->getNumBits() < 64) {
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RegOffset += 1;
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return ABIArgInfo::getExtend(Ty);
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}
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// Other non-aggregates go in registers.
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if (!isAggregateTypeForABI(Ty)) {
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RegOffset += Size / 64;
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return ABIArgInfo::getDirect();
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}
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// If a C++ object has either a non-trivial copy constructor or a non-trivial
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// destructor, it is passed with an explicit indirect pointer / sret pointer.
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if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) {
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RegOffset += 1;
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return getNaturalAlignIndirect(Ty, getDataLayout().getAllocaAddrSpace(),
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RAA == CGCXXABI::RAA_DirectInMemory);
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}
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// This is a small aggregate type that should be passed in registers.
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// Build a coercion type from the LLVM struct type.
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llvm::StructType *StrTy = dyn_cast<llvm::StructType>(CGT.ConvertType(Ty));
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if (!StrTy) {
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RegOffset += Size / 64;
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return ABIArgInfo::getDirect();
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}
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CoerceBuilder CB(VMContext, getDataLayout());
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CB.addStruct(0, StrTy);
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// All structs, even empty ones, should take up a register argument slot,
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// so pin the minimum struct size to one bit.
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CB.pad(llvm::alignTo(
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std::max(CB.DL.getTypeSizeInBits(StrTy).getKnownMinValue(), uint64_t(1)),
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64));
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RegOffset += CB.Size / 64;
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// If we're dealing with overaligned structs we may need to add a padding in
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// the front, to preserve the correct register-memory mapping.
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//
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// See SCD 2.4.1, pages 3P-11 and 3P-12.
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llvm::Type *Padding =
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NeedPadding ? llvm::Type::getInt64Ty(VMContext) : nullptr;
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RegOffset += NeedPadding ? 1 : 0;
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// Try to use the original type for coercion.
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llvm::Type *CoerceTy = CB.isUsableType(StrTy) ? StrTy : CB.getType();
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ABIArgInfo AAI = ABIArgInfo::getDirect(CoerceTy, 0, Padding);
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AAI.setInReg(CB.InReg);
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return AAI;
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}
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RValue SparcV9ABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr,
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QualType Ty, AggValueSlot Slot) const {
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CharUnits SlotSize = CharUnits::fromQuantity(8);
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auto TInfo = getContext().getTypeInfoInChars(Ty);
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// Zero-sized types have a width of one byte for parameter passing purposes.
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TInfo.Width = std::max(TInfo.Width, CharUnits::fromQuantity(1));
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// Arguments bigger than 2*SlotSize bytes are passed indirectly.
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return emitVoidPtrVAArg(CGF, VAListAddr, Ty,
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/*IsIndirect=*/TInfo.Width > 2 * SlotSize, TInfo,
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SlotSize,
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/*AllowHigherAlign=*/true, Slot);
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}
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void SparcV9ABIInfo::computeInfo(CGFunctionInfo &FI) const {
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unsigned RetOffset = 0;
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ABIArgInfo RetType = classifyType(FI.getReturnType(), 32 * 8, RetOffset);
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FI.getReturnInfo() = RetType;
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// Indirect returns will have its pointer passed as an argument.
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unsigned ArgOffset = RetType.isIndirect() ? RetOffset : 0;
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for (auto &I : FI.arguments())
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I.info = classifyType(I.type, 16 * 8, ArgOffset);
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}
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namespace {
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class SparcV9TargetCodeGenInfo : public TargetCodeGenInfo {
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public:
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SparcV9TargetCodeGenInfo(CodeGenTypes &CGT)
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: TargetCodeGenInfo(std::make_unique<SparcV9ABIInfo>(CGT)) {}
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int getDwarfEHStackPointer(CodeGen::CodeGenModule &M) const override {
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return 14;
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}
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bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override;
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llvm::Value *decodeReturnAddress(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override {
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return CGF.Builder.CreateGEP(CGF.Int8Ty, Address,
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llvm::ConstantInt::get(CGF.Int32Ty, 8));
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}
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llvm::Value *encodeReturnAddress(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const override {
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return CGF.Builder.CreateGEP(CGF.Int8Ty, Address,
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llvm::ConstantInt::get(CGF.Int32Ty, -8));
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}
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};
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} // end anonymous namespace
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bool
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SparcV9TargetCodeGenInfo::initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF,
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llvm::Value *Address) const {
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// This is calculated from the LLVM and GCC tables and verified
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// against gcc output. AFAIK all ABIs use the same encoding.
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CodeGen::CGBuilderTy &Builder = CGF.Builder;
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llvm::IntegerType *i8 = CGF.Int8Ty;
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llvm::Value *Four8 = llvm::ConstantInt::get(i8, 4);
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llvm::Value *Eight8 = llvm::ConstantInt::get(i8, 8);
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// 0-31: the 8-byte general-purpose registers
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AssignToArrayRange(Builder, Address, Eight8, 0, 31);
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// 32-63: f0-31, the 4-byte floating-point registers
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AssignToArrayRange(Builder, Address, Four8, 32, 63);
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// Y = 64
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// PSR = 65
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// WIM = 66
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// TBR = 67
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// PC = 68
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// NPC = 69
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// FSR = 70
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// CSR = 71
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AssignToArrayRange(Builder, Address, Eight8, 64, 71);
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// 72-87: d0-15, the 8-byte floating-point registers
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AssignToArrayRange(Builder, Address, Eight8, 72, 87);
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return false;
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}
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std::unique_ptr<TargetCodeGenInfo>
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CodeGen::createSparcV8TargetCodeGenInfo(CodeGenModule &CGM) {
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return std::make_unique<SparcV8TargetCodeGenInfo>(CGM.getTypes());
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}
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std::unique_ptr<TargetCodeGenInfo>
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CodeGen::createSparcV9TargetCodeGenInfo(CodeGenModule &CGM) {
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return std::make_unique<SparcV9TargetCodeGenInfo>(CGM.getTypes());
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}
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