efb57947ba
Summary: We support variadic functions in AMDGPU / NVPTX via an LLVM-IR pass. This patch applies the same handling here to support them on this target. I am unsure what the ABI should look like here, I have mostly copied the one we use for NVPTX where it's basically a struct layout with natural alignment. This wastes some space, which is why AMDGPU does not pad them. Additionally, this required allowing the SPIRV_FUNC calling convention. I'm assuming this is compatible with the C calling convention in IR, but I will need someone to confirm that for me.
77 lines
3.7 KiB
C
77 lines
3.7 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 6
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// RUN: %clang_cc1 -triple spirv64 -emit-llvm -o - %s | FileCheck %s
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extern void varargs_simple(int, ...);
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// CHECK-LABEL: define spir_func void @foo(
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// CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[C:%.*]] = alloca i8, align 1
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// CHECK-NEXT: [[S:%.*]] = alloca i16, align 2
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// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4
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// CHECK-NEXT: [[L:%.*]] = alloca i64, align 8
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// CHECK-NEXT: [[F:%.*]] = alloca float, align 4
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// CHECK-NEXT: [[D:%.*]] = alloca double, align 8
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// CHECK-NEXT: [[A:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4
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// CHECK-NEXT: [[V:%.*]] = alloca <4 x i32>, align 16
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// CHECK-NEXT: [[T:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 1
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// CHECK-NEXT: store i8 1, ptr [[C]], align 1
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// CHECK-NEXT: store i16 1, ptr [[S]], align 2
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// CHECK-NEXT: store i32 1, ptr [[I]], align 4
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// CHECK-NEXT: store i64 1, ptr [[L]], align 8
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// CHECK-NEXT: store float 1.000000e+00, ptr [[F]], align 4
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// CHECK-NEXT: store double 1.000000e+00, ptr [[D]], align 8
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// CHECK-NEXT: [[TMP0:%.*]] = load i8, ptr [[C]], align 1
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// CHECK-NEXT: [[CONV:%.*]] = sext i8 [[TMP0]] to i32
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// CHECK-NEXT: [[TMP1:%.*]] = load i16, ptr [[S]], align 2
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// CHECK-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
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// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[I]], align 4
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// CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[L]], align 8
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// CHECK-NEXT: [[TMP4:%.*]] = load float, ptr [[F]], align 4
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// CHECK-NEXT: [[CONV2:%.*]] = fpext float [[TMP4]] to double
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// CHECK-NEXT: [[TMP5:%.*]] = load double, ptr [[D]], align 8
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// CHECK-NEXT: call spir_func void (i32, ...) @varargs_simple(i32 noundef 0, i32 noundef [[CONV]], i32 noundef [[CONV1]], i32 noundef [[TMP2]], i64 noundef [[TMP3]], double noundef [[CONV2]], double noundef [[TMP5]])
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// CHECK-NEXT: call void @llvm.memcpy.p0.p1.i64(ptr align 4 [[A]], ptr addrspace(1) align 4 @__const.foo.a, i64 12, i1 false)
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// CHECK-NEXT: call spir_func void (i32, ...) @varargs_simple(i32 noundef 0, ptr noundef byval([[STRUCT_ANON]]) align 4 [[A]])
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// CHECK-NEXT: store <4 x i32> splat (i32 1), ptr [[V]], align 16
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// CHECK-NEXT: [[TMP6:%.*]] = load <4 x i32>, ptr [[V]], align 16
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// CHECK-NEXT: call spir_func void (i32, ...) @varargs_simple(i32 noundef 0, <4 x i32> noundef [[TMP6]])
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// CHECK-NEXT: call spir_func void (i32, ...) @varargs_simple(i32 noundef 0, ptr noundef byval([[STRUCT_ANON_0]]) align 1 [[T]], ptr noundef byval([[STRUCT_ANON_0]]) align 1 [[T]], i32 noundef 0, ptr noundef byval([[STRUCT_ANON_0]]) align 1 [[T]])
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// CHECK-NEXT: ret void
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//
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void foo() {
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char c = '\x1';
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short s = 1;
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int i = 1;
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long l = 1;
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float f = 1.f;
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double d = 1.;
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varargs_simple(0, c, s, i, l, f, d);
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struct {int x; char c; int y;} a = {1, '\x1', 1};
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varargs_simple(0, a);
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typedef int __attribute__((ext_vector_type(4))) int4;
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int4 v = {1, 1, 1, 1};
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varargs_simple(0, v);
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struct {char c, d;} t;
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varargs_simple(0, t, t, 0, t);
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}
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typedef struct {long x; long y;} S;
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extern void varargs_complex(S, S, ...);
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// CHECK-LABEL: define spir_func void @bar(
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// CHECK-SAME: ) #[[ATTR0]] {
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// CHECK-NEXT: [[ENTRY:.*:]]
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// CHECK-NEXT: [[S:%.*]] = alloca [[STRUCT_S:%.*]], align 8
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// CHECK-NEXT: call void @llvm.memcpy.p0.p1.i64(ptr align 8 [[S]], ptr addrspace(1) align 8 @__const.bar.s, i64 16, i1 false)
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// CHECK-NEXT: call spir_func void (ptr, ptr, ...) @varargs_complex(ptr noundef byval([[STRUCT_S]]) align 8 [[S]], ptr noundef byval([[STRUCT_S]]) align 8 [[S]], i32 noundef 1, i64 noundef 1, double noundef 1.000000e+00)
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// CHECK-NEXT: ret void
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//
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void bar() {
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S s = {1l, 1l};
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varargs_complex(s, s, 1, 1l, 1.0);
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}
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