7f7d78d05c
This patch adds a missing guard to the AArch64 ConditionOptimizer pass Previously, the cross-block optimization would not check for register equivalence before modifying the two comparison instructions. This means that two cmp instructions with suitable cond codes and immediates would be modified, even if their registers were different, which would not trigger CSE afterwards. This doesn't affect correctness but is unhelpful. A negative ll test and mir tests has also been added to confirm this fix.
625 lines
22 KiB
C++
625 lines
22 KiB
C++
//=- AArch64ConditionOptimizer.cpp - Remove useless comparisons for AArch64 -=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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// This pass tries to make consecutive comparisons of values use the same
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// operands to allow the CSE pass to remove duplicate instructions. It adjusts
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// comparisons with immediate values by converting between inclusive and
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// exclusive forms (GE <-> GT, LE <-> LT) and correcting immediate values to
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// make them equal.
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//
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// The pass handles:
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// * Cross-block: SUBS/ADDS followed by conditional branches
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// * Intra-block: CSINC conditional instructions
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//
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//
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// Consider the following example in C:
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//
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// if ((a < 5 && ...) || (a > 5 && ...)) {
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// ~~~~~ ~~~~~
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// ^ ^
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// x y
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//
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// Here both "x" and "y" expressions compare "a" with "5". When "x" evaluates
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// to "false", "y" can just check flags set by the first comparison. As a
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// result of the canonicalization employed by
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// SelectionDAGBuilder::visitSwitchCase, DAGCombine, and other target-specific
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// code, assembly ends up in the form that is not CSE friendly:
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//
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// ...
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// cmp w8, #4
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// b.gt .LBB0_3
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// ...
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// .LBB0_3:
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// cmp w8, #6
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// b.lt .LBB0_6
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// ...
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//
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// Same assembly after the pass:
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//
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// ...
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// cmp w8, #5
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// b.ge .LBB0_3
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// ...
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// .LBB0_3:
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// cmp w8, #5 // <-- CSE pass removes this instruction
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// b.le .LBB0_6
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// ...
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//
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// See optimizeCrossBlock() and optimizeIntraBlock() for implementation details.
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//
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// TODO: maybe handle TBNZ/TBZ the same way as CMP when used instead for "a < 0"
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// TODO: For cross-block:
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// - handle other conditional instructions (e.g. CSET)
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// - allow second branching to be anything if it doesn't require adjusting
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// TODO: For intra-block:
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// - handle CINC and CSET (CSINC aliases) as their conditions are inverted
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// compared to CSINC.
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// - handle other non-CSINC conditional instructions
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//
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//===----------------------------------------------------------------------===//
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#include "AArch64.h"
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#include "MCTargetDesc/AArch64AddressingModes.h"
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#include "Utils/AArch64BaseInfo.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineDominators.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/TargetInstrInfo.h"
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#include "llvm/CodeGen/TargetRegisterInfo.h"
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/InitializePasses.h"
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#include "llvm/Pass.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include <cassert>
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#include <cstdlib>
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#include <tuple>
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using namespace llvm;
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#define DEBUG_TYPE "aarch64-condopt"
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STATISTIC(NumConditionsAdjusted, "Number of conditions adjusted");
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namespace {
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class AArch64ConditionOptimizer : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineDominatorTree *DomTree;
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const MachineRegisterInfo *MRI;
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public:
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// Stores immediate, compare instruction opcode and branch condition (in this
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// order) of adjusted comparison.
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using CmpInfo = std::tuple<int, unsigned, AArch64CC::CondCode>;
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static char ID;
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AArch64ConditionOptimizer() : MachineFunctionPass(ID) {}
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void getAnalysisUsage(AnalysisUsage &AU) const override;
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MachineInstr *findSuitableCompare(MachineBasicBlock *MBB);
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CmpInfo adjustCmp(MachineInstr *CmpMI, AArch64CC::CondCode Cmp);
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void modifyCmp(MachineInstr *CmpMI, const CmpInfo &Info);
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bool adjustTo(MachineInstr *CmpMI, AArch64CC::CondCode Cmp, MachineInstr *To,
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int ToImm);
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bool isPureCmp(MachineInstr &CmpMI);
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bool optimizeIntraBlock(MachineBasicBlock &MBB);
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bool optimizeCrossBlock(MachineBasicBlock &HBB);
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "AArch64 Condition Optimizer";
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}
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};
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} // end anonymous namespace
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char AArch64ConditionOptimizer::ID = 0;
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INITIALIZE_PASS_BEGIN(AArch64ConditionOptimizer, "aarch64-condopt",
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"AArch64 CondOpt Pass", false, false)
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INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
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INITIALIZE_PASS_END(AArch64ConditionOptimizer, "aarch64-condopt",
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"AArch64 CondOpt Pass", false, false)
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FunctionPass *llvm::createAArch64ConditionOptimizerPass() {
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return new AArch64ConditionOptimizer();
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}
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void AArch64ConditionOptimizer::getAnalysisUsage(AnalysisUsage &AU) const {
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AU.addRequired<MachineDominatorTreeWrapperPass>();
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AU.addPreserved<MachineDominatorTreeWrapperPass>();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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// Finds compare instruction that corresponds to supported types of branching.
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// Returns the instruction or nullptr on failures or detecting unsupported
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// instructions.
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MachineInstr *AArch64ConditionOptimizer::findSuitableCompare(
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MachineBasicBlock *MBB) {
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MachineBasicBlock::iterator Term = MBB->getFirstTerminator();
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if (Term == MBB->end())
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return nullptr;
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if (Term->getOpcode() != AArch64::Bcc)
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return nullptr;
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// Since we may modify cmp of this MBB, make sure NZCV does not live out.
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for (auto *SuccBB : MBB->successors())
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if (SuccBB->isLiveIn(AArch64::NZCV))
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return nullptr;
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// Now find the instruction controlling the terminator.
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for (MachineBasicBlock::iterator B = MBB->begin(), It = Term; It != B;) {
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It = prev_nodbg(It, B);
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MachineInstr &I = *It;
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assert(!I.isTerminator() && "Spurious terminator");
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// Check if there is any use of NZCV between CMP and Bcc.
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if (I.readsRegister(AArch64::NZCV, /*TRI=*/nullptr))
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return nullptr;
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switch (I.getOpcode()) {
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// cmp is an alias for subs with a dead destination register.
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case AArch64::SUBSWri:
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case AArch64::SUBSXri:
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// cmn is an alias for adds with a dead destination register.
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case AArch64::ADDSWri:
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case AArch64::ADDSXri: {
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unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm());
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if (!I.getOperand(2).isImm()) {
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LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << I << '\n');
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return nullptr;
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} else if (I.getOperand(2).getImm() << ShiftAmt >= 0xfff) {
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LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << I
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<< '\n');
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return nullptr;
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} else if (!MRI->use_nodbg_empty(I.getOperand(0).getReg())) {
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LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << I << '\n');
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return nullptr;
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}
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return &I;
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}
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}
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if (I.modifiesRegister(AArch64::NZCV, /*TRI=*/nullptr))
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return nullptr;
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}
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LLVM_DEBUG(dbgs() << "Flags not defined in " << printMBBReference(*MBB)
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<< '\n');
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return nullptr;
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}
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// Changes opcode adds <-> subs considering register operand width.
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static int getComplementOpc(int Opc) {
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switch (Opc) {
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case AArch64::ADDSWri: return AArch64::SUBSWri;
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case AArch64::ADDSXri: return AArch64::SUBSXri;
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case AArch64::SUBSWri: return AArch64::ADDSWri;
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case AArch64::SUBSXri: return AArch64::ADDSXri;
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default:
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llvm_unreachable("Unexpected opcode");
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}
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}
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// Changes form of comparison inclusive <-> exclusive.
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static AArch64CC::CondCode getAdjustedCmp(AArch64CC::CondCode Cmp) {
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switch (Cmp) {
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case AArch64CC::GT: return AArch64CC::GE;
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case AArch64CC::GE: return AArch64CC::GT;
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case AArch64CC::LT: return AArch64CC::LE;
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case AArch64CC::LE: return AArch64CC::LT;
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default:
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llvm_unreachable("Unexpected condition code");
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}
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}
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// Transforms GT -> GE, GE -> GT, LT -> LE, LE -> LT by updating comparison
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// operator and condition code.
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AArch64ConditionOptimizer::CmpInfo AArch64ConditionOptimizer::adjustCmp(
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MachineInstr *CmpMI, AArch64CC::CondCode Cmp) {
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unsigned Opc = CmpMI->getOpcode();
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// CMN (compare with negative immediate) is an alias to ADDS (as
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// "operand - negative" == "operand + positive")
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bool Negative = (Opc == AArch64::ADDSWri || Opc == AArch64::ADDSXri);
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int Correction = (Cmp == AArch64CC::GT) ? 1 : -1;
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// Negate Correction value for comparison with negative immediate (CMN).
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if (Negative) {
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Correction = -Correction;
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}
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const int OldImm = (int)CmpMI->getOperand(2).getImm();
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const int NewImm = std::abs(OldImm + Correction);
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// Handle +0 -> -1 and -0 -> +1 (CMN with 0 immediate) transitions by
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// adjusting compare instruction opcode.
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if (OldImm == 0 && ((Negative && Correction == 1) ||
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(!Negative && Correction == -1))) {
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Opc = getComplementOpc(Opc);
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}
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return CmpInfo(NewImm, Opc, getAdjustedCmp(Cmp));
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}
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// Applies changes to comparison instruction suggested by adjustCmp().
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void AArch64ConditionOptimizer::modifyCmp(MachineInstr *CmpMI,
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const CmpInfo &Info) {
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int Imm;
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unsigned Opc;
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AArch64CC::CondCode Cmp;
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std::tie(Imm, Opc, Cmp) = Info;
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MachineBasicBlock *const MBB = CmpMI->getParent();
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// Change immediate in comparison instruction (ADDS or SUBS).
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BuildMI(*MBB, CmpMI, CmpMI->getDebugLoc(), TII->get(Opc))
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.add(CmpMI->getOperand(0))
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.add(CmpMI->getOperand(1))
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.addImm(Imm)
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.add(CmpMI->getOperand(3));
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CmpMI->eraseFromParent();
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// The fact that this comparison was picked ensures that it's related to the
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// first terminator instruction.
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MachineInstr &BrMI = *MBB->getFirstTerminator();
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// Change condition in branch instruction.
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BuildMI(*MBB, BrMI, BrMI.getDebugLoc(), TII->get(AArch64::Bcc))
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.addImm(Cmp)
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.add(BrMI.getOperand(1));
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BrMI.eraseFromParent();
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++NumConditionsAdjusted;
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}
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// Parse a condition code returned by analyzeBranch, and compute the CondCode
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// corresponding to TBB.
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// Returns true if parsing was successful, otherwise false is returned.
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static bool parseCond(ArrayRef<MachineOperand> Cond, AArch64CC::CondCode &CC) {
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// A normal br.cond simply has the condition code.
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if (Cond[0].getImm() != -1) {
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assert(Cond.size() == 1 && "Unknown Cond array format");
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CC = (AArch64CC::CondCode)(int)Cond[0].getImm();
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return true;
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}
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return false;
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}
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// Adjusts one cmp instruction to another one if result of adjustment will allow
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// CSE. Returns true if compare instruction was changed, otherwise false is
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// returned.
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bool AArch64ConditionOptimizer::adjustTo(MachineInstr *CmpMI,
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AArch64CC::CondCode Cmp, MachineInstr *To, int ToImm)
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{
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CmpInfo Info = adjustCmp(CmpMI, Cmp);
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if (std::get<0>(Info) == ToImm && std::get<1>(Info) == To->getOpcode()) {
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modifyCmp(CmpMI, Info);
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return true;
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}
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return false;
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}
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bool AArch64ConditionOptimizer::isPureCmp(MachineInstr &CmpMI) {
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unsigned ShiftAmt = AArch64_AM::getShiftValue(CmpMI.getOperand(3).getImm());
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if (!CmpMI.getOperand(2).isImm()) {
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LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << CmpMI << '\n');
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return false;
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} else if (CmpMI.getOperand(2).getImm() << ShiftAmt >= 0xfff) {
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LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << CmpMI
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<< '\n');
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return false;
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} else if (!MRI->use_nodbg_empty(CmpMI.getOperand(0).getReg())) {
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LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << CmpMI << '\n');
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return false;
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}
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return true;
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}
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// This function transforms two CMP+CSINC pairs within the same basic block
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// when both conditions are the same (GT/GT or LT/LT) and immediates differ
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// by 1.
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//
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// Example transformation:
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// cmp w8, #10
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// csinc w9, w0, w1, gt ; w9 = (w8 > 10) ? w0 : w1+1
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// cmp w8, #9
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// csinc w10, w0, w1, gt ; w10 = (w8 > 9) ? w0 : w1+1
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//
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// Into:
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// cmp w8, #10
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// csinc w9, w0, w1, gt ; w9 = (w8 > 10) ? w0 : w1+1
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// csinc w10, w0, w1, ge ; w10 = (w8 >= 10) ? w0 : w1+1
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//
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// The second CMP is eliminated, enabling CSE to remove the redundant
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// comparison.
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bool AArch64ConditionOptimizer::optimizeIntraBlock(MachineBasicBlock &MBB) {
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MachineInstr *FirstCmp = nullptr;
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MachineInstr *FirstCSINC = nullptr;
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MachineInstr *SecondCmp = nullptr;
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MachineInstr *SecondCSINC = nullptr;
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// Find two CMP + CSINC pairs
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for (MachineInstr &MI : MBB) {
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switch (MI.getOpcode()) {
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// cmp is an alias for subs with a dead destination register.
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case AArch64::SUBSWri:
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case AArch64::SUBSXri:
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// cmn is an alias for adds with a dead destination register.
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case AArch64::ADDSWri:
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case AArch64::ADDSXri: {
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if (!FirstCmp) {
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FirstCmp = &MI;
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} else if (FirstCSINC && !SecondCmp) {
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SecondCmp = &MI;
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}
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break;
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}
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case AArch64::CSINCWr:
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case AArch64::CSINCXr: {
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// Found a CSINC, ensure it comes after the corresponding comparison
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if (FirstCmp && !FirstCSINC) {
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FirstCSINC = &MI;
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} else if (SecondCmp && !SecondCSINC) {
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SecondCSINC = &MI;
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}
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break;
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}
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}
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if (SecondCSINC)
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break;
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}
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if (!SecondCmp || !SecondCSINC) {
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LLVM_DEBUG(dbgs() << "Didn't find two CMP+CSINC pairs\n");
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return false;
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}
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if (FirstCmp->getOperand(1).getReg() != SecondCmp->getOperand(1).getReg()) {
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LLVM_DEBUG(dbgs() << "CMPs compare different registers\n");
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return false;
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}
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if (!isPureCmp(*FirstCmp) || !isPureCmp(*SecondCmp)) {
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LLVM_DEBUG(dbgs() << "One or both CMPs are not pure\n");
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return false;
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}
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// Check that nothing else modifies the flags between the first CMP and second
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// conditional
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for (auto It = std::next(MachineBasicBlock::iterator(FirstCmp));
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It != std::next(MachineBasicBlock::iterator(SecondCSINC)); ++It) {
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if (&*It != SecondCmp &&
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It->modifiesRegister(AArch64::NZCV, /*TRI=*/nullptr)) {
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LLVM_DEBUG(dbgs() << "Flags modified between CMPs by: " << *It << '\n');
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return false;
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}
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}
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// Check flags aren't read after second conditional within the same block
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for (auto It = std::next(MachineBasicBlock::iterator(SecondCSINC));
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It != MBB.end(); ++It) {
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if (It->readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) {
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LLVM_DEBUG(dbgs() << "Flags read after second CSINC by: " << *It << '\n');
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return false;
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}
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}
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// Since we may modify a cmp in this MBB, make sure NZCV does not live out.
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for (auto *SuccBB : MBB.successors())
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if (SuccBB->isLiveIn(AArch64::NZCV))
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return false;
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// Extract condition codes from both CSINCs (operand 3)
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AArch64CC::CondCode FirstCond =
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(AArch64CC::CondCode)(int)FirstCSINC->getOperand(3).getImm();
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AArch64CC::CondCode SecondCond =
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(AArch64CC::CondCode)(int)SecondCSINC->getOperand(3).getImm();
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const int FirstImm = (int)FirstCmp->getOperand(2).getImm();
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const int SecondImm = (int)SecondCmp->getOperand(2).getImm();
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LLVM_DEBUG(dbgs() << "Comparing intra-block CSINCs: "
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<< AArch64CC::getCondCodeName(FirstCond) << " #" << FirstImm
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<< " and " << AArch64CC::getCondCodeName(SecondCond) << " #"
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<< SecondImm << '\n');
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// Check if both conditions are the same and immediates differ by 1
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if (((FirstCond == AArch64CC::GT && SecondCond == AArch64CC::GT) ||
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(FirstCond == AArch64CC::LT && SecondCond == AArch64CC::LT)) &&
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std::abs(SecondImm - FirstImm) == 1) {
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// Pick which comparison to adjust to match the other
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// For GT: adjust the one with smaller immediate
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// For LT: adjust the one with larger immediate
|
|
bool adjustFirst = (FirstImm < SecondImm);
|
|
if (FirstCond == AArch64CC::LT) {
|
|
adjustFirst = !adjustFirst;
|
|
}
|
|
|
|
MachineInstr *CmpToAdjust = adjustFirst ? FirstCmp : SecondCmp;
|
|
MachineInstr *CSINCToAdjust = adjustFirst ? FirstCSINC : SecondCSINC;
|
|
AArch64CC::CondCode CondToAdjust = adjustFirst ? FirstCond : SecondCond;
|
|
int TargetImm = adjustFirst ? SecondImm : FirstImm;
|
|
|
|
CmpInfo AdjustedInfo = adjustCmp(CmpToAdjust, CondToAdjust);
|
|
|
|
if (std::get<0>(AdjustedInfo) == TargetImm &&
|
|
std::get<1>(AdjustedInfo) ==
|
|
(adjustFirst ? SecondCmp : FirstCmp)->getOpcode()) {
|
|
LLVM_DEBUG(dbgs() << "Successfully optimizing intra-block CSINC pair\n");
|
|
|
|
// Modify the selected CMP and CSINC
|
|
CmpToAdjust->getOperand(2).setImm(std::get<0>(AdjustedInfo));
|
|
CmpToAdjust->setDesc(TII->get(std::get<1>(AdjustedInfo)));
|
|
CSINCToAdjust->getOperand(3).setImm(std::get<2>(AdjustedInfo));
|
|
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
// Optimize across blocks
|
|
bool AArch64ConditionOptimizer::optimizeCrossBlock(MachineBasicBlock &HBB) {
|
|
SmallVector<MachineOperand, 4> HeadCond;
|
|
MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
|
|
if (TII->analyzeBranch(HBB, TBB, FBB, HeadCond)) {
|
|
return false;
|
|
}
|
|
|
|
// Equivalence check is to skip loops.
|
|
if (!TBB || TBB == &HBB) {
|
|
return false;
|
|
}
|
|
|
|
SmallVector<MachineOperand, 4> TrueCond;
|
|
MachineBasicBlock *TBB_TBB = nullptr, *TBB_FBB = nullptr;
|
|
if (TII->analyzeBranch(*TBB, TBB_TBB, TBB_FBB, TrueCond)) {
|
|
return false;
|
|
}
|
|
|
|
MachineInstr *HeadCmpMI = findSuitableCompare(&HBB);
|
|
if (!HeadCmpMI) {
|
|
return false;
|
|
}
|
|
|
|
MachineInstr *TrueCmpMI = findSuitableCompare(TBB);
|
|
if (!TrueCmpMI) {
|
|
return false;
|
|
}
|
|
|
|
// Ensure both compares use the same register, tracing through copies.
|
|
Register HeadReg = HeadCmpMI->getOperand(1).getReg();
|
|
Register TrueReg = TrueCmpMI->getOperand(1).getReg();
|
|
Register HeadCmpReg =
|
|
HeadReg.isVirtual() ? TRI->lookThruCopyLike(HeadReg, MRI) : HeadReg;
|
|
Register TrueCmpReg =
|
|
TrueReg.isVirtual() ? TRI->lookThruCopyLike(TrueReg, MRI) : TrueReg;
|
|
if (HeadCmpReg != TrueCmpReg) {
|
|
LLVM_DEBUG(dbgs() << "CMPs compare different registers\n");
|
|
return false;
|
|
}
|
|
|
|
AArch64CC::CondCode HeadCmp;
|
|
if (HeadCond.empty() || !parseCond(HeadCond, HeadCmp)) {
|
|
return false;
|
|
}
|
|
|
|
AArch64CC::CondCode TrueCmp;
|
|
if (TrueCond.empty() || !parseCond(TrueCond, TrueCmp)) {
|
|
return false;
|
|
}
|
|
|
|
const int HeadImm = (int)HeadCmpMI->getOperand(2).getImm();
|
|
const int TrueImm = (int)TrueCmpMI->getOperand(2).getImm();
|
|
|
|
LLVM_DEBUG(dbgs() << "Head branch:\n");
|
|
LLVM_DEBUG(dbgs() << "\tcondition: " << AArch64CC::getCondCodeName(HeadCmp)
|
|
<< '\n');
|
|
LLVM_DEBUG(dbgs() << "\timmediate: " << HeadImm << '\n');
|
|
|
|
LLVM_DEBUG(dbgs() << "True branch:\n");
|
|
LLVM_DEBUG(dbgs() << "\tcondition: " << AArch64CC::getCondCodeName(TrueCmp)
|
|
<< '\n');
|
|
LLVM_DEBUG(dbgs() << "\timmediate: " << TrueImm << '\n');
|
|
|
|
if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::LT) ||
|
|
(HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::GT)) &&
|
|
std::abs(TrueImm - HeadImm) == 2) {
|
|
// This branch transforms machine instructions that correspond to
|
|
//
|
|
// 1) (a > {TrueImm} && ...) || (a < {HeadImm} && ...)
|
|
// 2) (a < {TrueImm} && ...) || (a > {HeadImm} && ...)
|
|
//
|
|
// into
|
|
//
|
|
// 1) (a >= {NewImm} && ...) || (a <= {NewImm} && ...)
|
|
// 2) (a <= {NewImm} && ...) || (a >= {NewImm} && ...)
|
|
|
|
CmpInfo HeadCmpInfo = adjustCmp(HeadCmpMI, HeadCmp);
|
|
CmpInfo TrueCmpInfo = adjustCmp(TrueCmpMI, TrueCmp);
|
|
if (std::get<0>(HeadCmpInfo) == std::get<0>(TrueCmpInfo) &&
|
|
std::get<1>(HeadCmpInfo) == std::get<1>(TrueCmpInfo)) {
|
|
modifyCmp(HeadCmpMI, HeadCmpInfo);
|
|
modifyCmp(TrueCmpMI, TrueCmpInfo);
|
|
return true;
|
|
}
|
|
} else if (((HeadCmp == AArch64CC::GT && TrueCmp == AArch64CC::GT) ||
|
|
(HeadCmp == AArch64CC::LT && TrueCmp == AArch64CC::LT)) &&
|
|
std::abs(TrueImm - HeadImm) == 1) {
|
|
// This branch transforms machine instructions that correspond to
|
|
//
|
|
// 1) (a > {TrueImm} && ...) || (a > {HeadImm} && ...)
|
|
// 2) (a < {TrueImm} && ...) || (a < {HeadImm} && ...)
|
|
//
|
|
// into
|
|
//
|
|
// 1) (a <= {NewImm} && ...) || (a > {NewImm} && ...)
|
|
// 2) (a < {NewImm} && ...) || (a >= {NewImm} && ...)
|
|
|
|
// GT -> GE transformation increases immediate value, so picking the
|
|
// smaller one; LT -> LE decreases immediate value so invert the choice.
|
|
bool adjustHeadCond = (HeadImm < TrueImm);
|
|
if (HeadCmp == AArch64CC::LT) {
|
|
adjustHeadCond = !adjustHeadCond;
|
|
}
|
|
|
|
if (adjustHeadCond) {
|
|
return adjustTo(HeadCmpMI, HeadCmp, TrueCmpMI, TrueImm);
|
|
} else {
|
|
return adjustTo(TrueCmpMI, TrueCmp, HeadCmpMI, HeadImm);
|
|
}
|
|
}
|
|
// Other transformation cases almost never occur due to generation of < or >
|
|
// comparisons instead of <= and >=.
|
|
|
|
return false;
|
|
}
|
|
|
|
bool AArch64ConditionOptimizer::runOnMachineFunction(MachineFunction &MF) {
|
|
LLVM_DEBUG(dbgs() << "********** AArch64 Conditional Compares **********\n"
|
|
<< "********** Function: " << MF.getName() << '\n');
|
|
if (skipFunction(MF.getFunction()))
|
|
return false;
|
|
|
|
TII = MF.getSubtarget().getInstrInfo();
|
|
TRI = MF.getSubtarget().getRegisterInfo();
|
|
DomTree = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
|
|
MRI = &MF.getRegInfo();
|
|
|
|
bool Changed = false;
|
|
|
|
// Visit blocks in dominator tree pre-order. The pre-order enables multiple
|
|
// cmp-conversions from the same head block.
|
|
// Note that updateDomTree() modifies the children of the DomTree node
|
|
// currently being visited. The df_iterator supports that; it doesn't look at
|
|
// child_begin() / child_end() until after a node has been visited.
|
|
for (MachineDomTreeNode *I : depth_first(DomTree)) {
|
|
MachineBasicBlock *HBB = I->getBlock();
|
|
Changed |= optimizeIntraBlock(*HBB);
|
|
Changed |= optimizeCrossBlock(*HBB);
|
|
}
|
|
|
|
return Changed;
|
|
}
|