ad1a45b903
Currently, when SDAG is run on AArch64 and an `optnone` function is encountered, the selector is chosen as FastISel. AArch64 makes use of GlobalISel at O0 and this patch aims to align `optnone` with this functionality. A flag is exposed to enable this functionality for a given backend but, as AArch64 is currently the only backend I could find using GlobalISel at O0 this is the only one with it implemented. This flag is set when the target supports GlobalISel & GlobalISel hasn't been forced by the user, the target machine or by being at an optimisation level lower than `EnableGlobalISelAtO`. If this happens, the GlobalISel passes are included as shown in `llvm/test/CodeGen/AArch64/O3-pipeline.ll` and skipped by IRTranslator for functions not marked as `optnone`. In updating the tests based on this functionality, I found some unused check lines or run lines that mixed SDAG with GlobalISel pass names which have been fixed. --------- Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
122 lines
4.3 KiB
C++
122 lines
4.3 KiB
C++
//==-- AArch64TargetMachine.h - Define TargetMachine for AArch64 -*- C++ -*-==//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This file declares the AArch64 specific subclass of TargetMachine.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
|
|
#define LLVM_LIB_TARGET_AARCH64_AARCH64TARGETMACHINE_H
|
|
|
|
#include "AArch64InstrInfo.h"
|
|
#include "AArch64Subtarget.h"
|
|
#include "llvm/CodeGen/CodeGenTargetMachineImpl.h"
|
|
#include "llvm/IR/DataLayout.h"
|
|
#include <optional>
|
|
|
|
namespace llvm {
|
|
|
|
class AArch64TargetMachine : public CodeGenTargetMachineImpl {
|
|
protected:
|
|
std::unique_ptr<TargetLoweringObjectFile> TLOF;
|
|
mutable StringMap<std::unique_ptr<AArch64Subtarget>> SubtargetMap;
|
|
|
|
/// Reset internal state.
|
|
void reset() override;
|
|
|
|
public:
|
|
AArch64TargetMachine(const Target &T, const Triple &TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
std::optional<Reloc::Model> RM,
|
|
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
|
|
bool JIT, bool IsLittleEndian);
|
|
|
|
~AArch64TargetMachine() override;
|
|
const AArch64Subtarget *getSubtargetImpl(const Function &F) const override;
|
|
// DO NOT IMPLEMENT: There is no such thing as a valid default subtarget,
|
|
// subtargets are per-function entities based on the target-specific
|
|
// attributes of each function.
|
|
const AArch64Subtarget *getSubtargetImpl() const = delete;
|
|
|
|
// Pass Pipeline Configuration
|
|
TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
|
|
|
|
void registerPassBuilderCallbacks(PassBuilder &PB) override;
|
|
|
|
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
|
|
|
|
TargetLoweringObjectFile* getObjFileLowering() const override {
|
|
return TLOF.get();
|
|
}
|
|
|
|
MachineFunctionInfo *
|
|
createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
|
|
const TargetSubtargetInfo *STI) const override;
|
|
|
|
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
|
|
yaml::MachineFunctionInfo *
|
|
convertFuncInfoToYAML(const MachineFunction &MF) const override;
|
|
bool parseMachineFunctionInfo(const yaml::MachineFunctionInfo &,
|
|
PerFunctionMIParsingState &PFS,
|
|
SMDiagnostic &Error,
|
|
SMRange &SourceRange) const override;
|
|
|
|
/// Returns true if a cast between SrcAS and DestAS is a noop.
|
|
bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
|
|
return getPointerSize(SrcAS) == getPointerSize(DestAS);
|
|
}
|
|
ScheduleDAGInstrs *
|
|
createMachineScheduler(MachineSchedContext *C) const override;
|
|
|
|
ScheduleDAGInstrs *
|
|
createPostMachineScheduler(MachineSchedContext *C) const override;
|
|
|
|
size_t clearLinkerOptimizationHints(
|
|
const SmallPtrSetImpl<MachineInstr *> &MIs) const override;
|
|
|
|
/// Returns true if the new SME ABI lowering should be used.
|
|
bool useNewSMEABILowering() const { return UseNewSMEABILowering; }
|
|
|
|
/// Returns the optimisation level that enables GlobalISel.
|
|
unsigned getEnableGlobalISelAtO() const;
|
|
|
|
private:
|
|
bool isLittle;
|
|
bool UseNewSMEABILowering;
|
|
};
|
|
|
|
// AArch64 little endian target machine.
|
|
//
|
|
class AArch64leTargetMachine : public AArch64TargetMachine {
|
|
virtual void anchor();
|
|
|
|
public:
|
|
AArch64leTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
std::optional<Reloc::Model> RM,
|
|
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
|
|
bool JIT);
|
|
};
|
|
|
|
// AArch64 big endian target machine.
|
|
//
|
|
class AArch64beTargetMachine : public AArch64TargetMachine {
|
|
virtual void anchor();
|
|
|
|
public:
|
|
AArch64beTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
|
|
StringRef FS, const TargetOptions &Options,
|
|
std::optional<Reloc::Model> RM,
|
|
std::optional<CodeModel::Model> CM, CodeGenOptLevel OL,
|
|
bool JIT);
|
|
};
|
|
|
|
} // end namespace llvm
|
|
|
|
#endif
|