f734cebc39
After overriding `TargetTransformInfo::enableMemCmpExpansion` in this commit, `MergeICmps` and `ExpandMemCmp` passes will be enabled on LoongArch.
136 lines
4.3 KiB
C++
136 lines
4.3 KiB
C++
//===-- LoongArchTargetTransformInfo.cpp - LoongArch specific TTI ---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements a TargetTransformInfo analysis pass specific to the
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/// LoongArch target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#include "LoongArchTargetTransformInfo.h"
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using namespace llvm;
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#define DEBUG_TYPE "loongarchtti"
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TypeSize LoongArchTTIImpl::getRegisterBitWidth(
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TargetTransformInfo::RegisterKind K) const {
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TypeSize DefSize = TargetTransformInfoImplBase::getRegisterBitWidth(K);
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switch (K) {
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case TargetTransformInfo::RGK_Scalar:
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return TypeSize::getFixed(ST->is64Bit() ? 64 : 32);
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case TargetTransformInfo::RGK_FixedWidthVector:
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if (ST->hasExtLASX())
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return TypeSize::getFixed(256);
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if (ST->hasExtLSX())
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return TypeSize::getFixed(128);
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[[fallthrough]];
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case TargetTransformInfo::RGK_ScalableVector:
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return DefSize;
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}
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llvm_unreachable("Unsupported register kind");
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}
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unsigned LoongArchTTIImpl::getNumberOfRegisters(unsigned ClassID) const {
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switch (ClassID) {
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case LoongArchRegisterClass::GPRRC:
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// 30 = 32 GPRs - r0 (zero register) - r21 (non-allocatable)
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return 30;
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case LoongArchRegisterClass::FPRRC:
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return ST->hasBasicF() ? 32 : 0;
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case LoongArchRegisterClass::VRRC:
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return ST->hasExtLSX() ? 32 : 0;
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}
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llvm_unreachable("unknown register class");
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}
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unsigned LoongArchTTIImpl::getRegisterClassForType(bool Vector,
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Type *Ty) const {
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if (Vector)
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return LoongArchRegisterClass::VRRC;
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if (!Ty)
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return LoongArchRegisterClass::GPRRC;
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Type *ScalarTy = Ty->getScalarType();
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if ((ScalarTy->isFloatTy() && ST->hasBasicF()) ||
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(ScalarTy->isDoubleTy() && ST->hasBasicD())) {
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return LoongArchRegisterClass::FPRRC;
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}
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return LoongArchRegisterClass::GPRRC;
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}
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unsigned LoongArchTTIImpl::getMaxInterleaveFactor(ElementCount VF) const {
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return ST->getMaxInterleaveFactor();
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}
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const char *LoongArchTTIImpl::getRegisterClassName(unsigned ClassID) const {
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switch (ClassID) {
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case LoongArchRegisterClass::GPRRC:
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return "LoongArch::GPRRC";
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case LoongArchRegisterClass::FPRRC:
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return "LoongArch::FPRRC";
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case LoongArchRegisterClass::VRRC:
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return "LoongArch::VRRC";
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}
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llvm_unreachable("unknown register class");
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}
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TargetTransformInfo::PopcntSupportKind
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LoongArchTTIImpl::getPopcntSupport(unsigned TyWidth) const {
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assert(isPowerOf2_32(TyWidth) && "Ty width must be power of 2");
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return ST->hasExtLSX() ? TTI::PSK_FastHardware : TTI::PSK_Software;
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}
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unsigned LoongArchTTIImpl::getCacheLineSize() const { return 64; }
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unsigned LoongArchTTIImpl::getPrefetchDistance() const { return 200; }
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bool LoongArchTTIImpl::enableWritePrefetching() const { return true; }
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bool LoongArchTTIImpl::shouldExpandReduction(const IntrinsicInst *II) const {
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switch (II->getIntrinsicID()) {
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default:
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return true;
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case Intrinsic::vector_reduce_add:
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case Intrinsic::vector_reduce_and:
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case Intrinsic::vector_reduce_or:
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case Intrinsic::vector_reduce_smax:
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case Intrinsic::vector_reduce_smin:
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case Intrinsic::vector_reduce_umax:
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case Intrinsic::vector_reduce_umin:
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case Intrinsic::vector_reduce_xor:
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return false;
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}
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}
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LoongArchTTIImpl::TTI::MemCmpExpansionOptions
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LoongArchTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
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TTI::MemCmpExpansionOptions Options;
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if (!ST->hasUAL())
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return Options;
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Options.MaxNumLoads = TLI->getMaxExpandSizeMemcmp(OptSize);
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Options.NumLoadsPerBlock = Options.MaxNumLoads;
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Options.AllowOverlappingLoads = true;
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// TODO: Support for vectors.
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if (ST->is64Bit()) {
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Options.LoadSizes = {8, 4, 2, 1};
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Options.AllowedTailExpansions = {3, 5, 6};
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} else {
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Options.LoadSizes = {4, 2, 1};
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Options.AllowedTailExpansions = {3};
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}
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return Options;
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}
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