ed3597e2f7
There are two classes of operands that DecoderEmitter cannot currently
handle:
1. Operands that do not participate in instruction encoding.
2. Operands whose encoding contains only 1s and 0s.
Because of this, targets developed various workarounds. Some targets
insert missing operands after an instruction has been (incompletely)
decoded, other take into account the missing operands when printing the
instruction. Some targets do neither of that and fail to correctly
disassemble some instructions.
This patch makes it possible to decode both classes of operands and
allows to remove existing workarounds.
For the case of operand with no contribution to instruction encoding,
one should now add `bits<0> OpName` field to instruction encoding
record. This will make DecoderEmitter generate a call to the decoder
function specified by the operand's DecoderMethod. The function has a
signature different from the usual one and looks like this:
```
static DecodeStatus DecodeImm42Operand(MCInst &Inst, const MCDisassembler *Decoder) {
Inst.addOperand(MCOperand::createImm(42));
return DecodeStatus::Success;
}
```
Notably, encoding bits are not passed to it (since there are none).
There is nothing special about the second case, the operand bits are
passed as usual. The difference is that before this change, the function
was not called if all the bits of the operand were known (no '?' in the
operand encoding).
There are two options controlling the behavior. Passing an option
enables the old behavior. They exist to allow smooth transition to the
new behavior. They are temporary (yeah, I know) and will be removed once
all targets migrate, possibly giving some more time to downstream
targets.
Subsequent patches in the stack enable the new behavior on some in-tree
targets.
184 lines
7.3 KiB
C++
184 lines
7.3 KiB
C++
//===-- M68kDisassembler.cpp - Disassembler for M68k ------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file is part of the M68k Disassembler.
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//
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//===----------------------------------------------------------------------===//
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#include "M68k.h"
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#include "M68kRegisterInfo.h"
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#include "M68kSubtarget.h"
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#include "MCTargetDesc/M68kMCCodeEmitter.h"
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#include "MCTargetDesc/M68kMCTargetDesc.h"
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#include "TargetInfo/M68kTargetInfo.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDecoder.h"
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#include "llvm/MC/MCDecoderOps.h"
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#include "llvm/MC/MCDisassembler/MCDisassembler.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Endian.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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using namespace llvm::MCD;
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#define DEBUG_TYPE "m68k-disassembler"
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typedef MCDisassembler::DecodeStatus DecodeStatus;
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static const unsigned RegisterDecode[] = {
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M68k::D0, M68k::D1, M68k::D2, M68k::D3, M68k::D4, M68k::D5,
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M68k::D6, M68k::D7, M68k::A0, M68k::A1, M68k::A2, M68k::A3,
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M68k::A4, M68k::A5, M68k::A6, M68k::SP, M68k::FP0, M68k::FP1,
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M68k::FP2, M68k::FP3, M68k::FP4, M68k::FP5, M68k::FP6, M68k::FP7,
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M68k::FPIAR, M68k::FPS, M68k::FPC};
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static DecodeStatus DecodeRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address, const void *Decoder) {
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if (RegNo >= 24)
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return DecodeStatus::Fail;
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Inst.addOperand(MCOperand::createReg(RegisterDecode[RegNo]));
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return DecodeStatus::Success;
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}
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static DecodeStatus DecodeDR32RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeDR16RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeDR8RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeAR32RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
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}
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static DecodeStatus DecodeAR16RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo | 8ULL, Address, Decoder);
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}
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static DecodeStatus DecodeXR32RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeXR16RegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo, Address, Decoder);
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}
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static DecodeStatus DecodeFPDRRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, RegNo | 16ULL, Address, Decoder);
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}
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#define DecodeFPDR32RegisterClass DecodeFPDRRegisterClass
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#define DecodeFPDR64RegisterClass DecodeFPDRRegisterClass
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#define DecodeFPDR80RegisterClass DecodeFPDRRegisterClass
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static DecodeStatus DecodeFPCSCRegisterClass(MCInst &Inst, uint64_t RegNo,
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uint64_t Address,
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const void *Decoder) {
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return DecodeRegisterClass(Inst, (RegNo >> 1) + 24, Address, Decoder);
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}
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#define DecodeFPICRegisterClass DecodeFPCSCRegisterClass
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static DecodeStatus DecodeCCRCRegisterClass(MCInst &Inst,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(M68k::CCR));
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return DecodeStatus::Success;
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}
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static DecodeStatus DecodeSRCRegisterClass(MCInst &Inst,
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const MCDisassembler *Decoder) {
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Inst.addOperand(MCOperand::createReg(M68k::SR));
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return DecodeStatus::Success;
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}
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static DecodeStatus DecodeImm32(MCInst &Inst, uint64_t Imm, uint64_t Address,
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const void *Decoder) {
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Inst.addOperand(MCOperand::createImm(M68k::swapWord<uint32_t>(Imm)));
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return DecodeStatus::Success;
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}
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#include "M68kGenDisassemblerTables.inc"
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#undef DecodeFPDR32RegisterClass
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#undef DecodeFPDR64RegisterClass
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#undef DecodeFPDR80RegisterClass
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#undef DecodeFPICRegisterClass
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/// A disassembler class for M68k.
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struct M68kDisassembler : public MCDisassembler {
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M68kDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
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: MCDisassembler(STI, Ctx) {}
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virtual ~M68kDisassembler() {}
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DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes, uint64_t Address,
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raw_ostream &CStream) const override;
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};
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DecodeStatus M68kDisassembler::getInstruction(MCInst &Instr, uint64_t &Size,
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ArrayRef<uint8_t> Bytes,
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uint64_t Address,
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raw_ostream &CStream) const {
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DecodeStatus Result;
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auto MakeUp = [&](APInt &Insn, unsigned InstrBits) {
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unsigned Idx = Insn.getBitWidth() >> 3;
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unsigned RoundUp = alignTo(InstrBits, Align(16));
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if (RoundUp > Insn.getBitWidth())
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Insn = Insn.zext(RoundUp);
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RoundUp = RoundUp >> 3;
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for (; Idx < RoundUp; Idx += 2) {
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Insn.insertBits(support::endian::read16be(&Bytes[Idx]), Idx * 8, 16);
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}
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};
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APInt Insn(16, support::endian::read16be(Bytes.data()));
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// 2 bytes of data are consumed, so set Size to 2
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// If we don't do this, disassembler may generate result even
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// the encoding is invalid. We need to let it fail correctly.
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Size = 2;
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Result = decodeInstruction(DecoderTable80, Instr, Insn, Address, this, STI,
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MakeUp);
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if (Result == DecodeStatus::Success)
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Size = InstrLenTable[Instr.getOpcode()] >> 3;
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return Result;
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}
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static MCDisassembler *createM68kDisassembler(const Target &T,
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const MCSubtargetInfo &STI,
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MCContext &Ctx) {
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return new M68kDisassembler(STI, Ctx);
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}
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extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeM68kDisassembler() {
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// Register the disassembler.
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TargetRegistry::RegisterMCDisassembler(getTheM68kTarget(),
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createM68kDisassembler);
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}
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