a6032d293c
This bug seems to have been exposed by the combined m->m load/store instructions available on M68k (these instructions are not available on i386, which the M68k backend is based on). This meant that token factors were inserted which could lead to distinct call sequence chains, increasing the nesting level and preventing the matching callseq_start from being identified during scheduling. The patch addresses this by not allowing combined loads/stores when the folded operation would result in a new chain dependency on a different call sequence. closes #146213 and #175472
1147 lines
34 KiB
C++
1147 lines
34 KiB
C++
//===-- M68kISelDAGToDAG.cpp - M68k Dag to Dag Inst Selector ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file defines an instruction selector for the M68K target.
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///
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//===----------------------------------------------------------------------===//
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#include "M68k.h"
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#include "M68kMachineFunction.h"
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#include "M68kRegisterInfo.h"
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#include "M68kSelectionDAGInfo.h"
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#include "M68kTargetMachine.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Alignment.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "m68k-isel"
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#define PASS_NAME "M68k DAG->DAG Pattern Instruction Selection"
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namespace {
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// For reference, the full order of operands for memory references is:
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// (Operand), Displacement, Base, Index, Scale
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struct M68kISelAddressMode {
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enum class AddrType {
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ARI, // Address Register Indirect
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ARIPI, // Address Register Indirect with Postincrement
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ARIPD, // Address Register Indirect with Postdecrement
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ARID, // Address Register Indirect with Displacement
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ARII, // Address Register Indirect with Index
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PCD, // Program Counter Indirect with Displacement
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PCI, // Program Counter Indirect with Index
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AL, // Absolute
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};
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AddrType AM;
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enum class Base { RegBase, FrameIndexBase };
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Base BaseType;
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int64_t Disp;
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// This is really a union, discriminated by BaseType!
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SDValue BaseReg;
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int BaseFrameIndex;
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SDValue IndexReg;
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unsigned Scale;
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const GlobalValue *GV;
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const Constant *CP;
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const BlockAddress *BlockAddr;
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const char *ES;
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MCSymbol *MCSym;
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int JT;
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Align Alignment; // CP alignment.
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unsigned char SymbolFlags; // M68kII::MO_*
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M68kISelAddressMode(AddrType AT)
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: AM(AT), BaseType(Base::RegBase), Disp(0), BaseFrameIndex(0), IndexReg(),
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Scale(1), GV(nullptr), CP(nullptr), BlockAddr(nullptr), ES(nullptr),
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MCSym(nullptr), JT(-1), Alignment(), SymbolFlags(M68kII::MO_NO_FLAG) {}
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bool hasSymbolicDisplacement() const {
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return GV != nullptr || CP != nullptr || ES != nullptr ||
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MCSym != nullptr || JT != -1 || BlockAddr != nullptr;
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}
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bool hasBase() const {
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return BaseType == Base::FrameIndexBase || BaseReg.getNode() != nullptr;
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}
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bool hasFrameIndex() const { return BaseType == Base::FrameIndexBase; }
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bool hasBaseReg() const {
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return BaseType == Base::RegBase && BaseReg.getNode() != nullptr;
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}
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bool hasIndexReg() const {
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return BaseType == Base::RegBase && IndexReg.getNode() != nullptr;
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}
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/// True if address mode type supports displacement
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bool isDispAddrType() const {
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return AM == AddrType::ARII || AM == AddrType::PCI ||
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AM == AddrType::ARID || AM == AddrType::PCD || AM == AddrType::AL;
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}
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unsigned getDispSize() const {
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switch (AM) {
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default:
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return 0;
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case AddrType::ARII:
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case AddrType::PCI:
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return 8;
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// These two in the next chip generations can hold upto 32 bit
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case AddrType::ARID:
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case AddrType::PCD:
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return 16;
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case AddrType::AL:
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return 32;
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}
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}
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bool hasDisp() const { return getDispSize() != 0; }
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bool isDisp8() const { return getDispSize() == 8; }
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bool isDisp16() const { return getDispSize() == 16; }
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bool isDisp32() const { return getDispSize() == 32; }
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/// Return true if this addressing mode is already PC-relative.
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bool isPCRelative() const {
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if (BaseType != Base::RegBase)
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return false;
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if (auto *RegNode = dyn_cast_or_null<RegisterSDNode>(BaseReg.getNode()))
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return RegNode->getReg() == M68k::PC;
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return false;
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}
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void setBaseReg(SDValue Reg) {
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BaseType = Base::RegBase;
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BaseReg = Reg;
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}
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void setIndexReg(SDValue Reg) { IndexReg = Reg; }
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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void dump() {
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dbgs() << "M68kISelAddressMode " << this;
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dbgs() << "\nDisp: " << Disp;
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dbgs() << ", BaseReg: ";
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if (BaseReg.getNode())
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BaseReg.getNode()->dump();
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else
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dbgs() << "null";
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dbgs() << ", BaseFI: " << BaseFrameIndex;
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dbgs() << ", IndexReg: ";
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if (IndexReg.getNode()) {
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IndexReg.getNode()->dump();
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} else {
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dbgs() << "null";
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dbgs() << ", Scale: " << Scale;
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}
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dbgs() << '\n';
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}
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#endif
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};
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} // end anonymous namespace
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namespace {
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// Helper type used by isSafeStoreLoad. Used to determine if
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// it is safe to fold a load and store into a single operation.
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struct CallSeqChainInfo {
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// The nearest callseq_{start/end} (or lowered equivalent)
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// in the chain of the load or store currently being analyzed.
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SDNode *Node = nullptr;
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// True when a TokenFactor introduces a dependency on more than one
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// chain with a callseq_{start/end} (or lowered equivalent) to the load
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// or store currently being analyzed
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bool Multiple = false;
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};
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static bool isCallSeqNode(const SDNode *N) {
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if (N->getOpcode() == ISD::CALLSEQ_START ||
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N->getOpcode() == ISD::CALLSEQ_END)
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return true;
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if (N->isMachineOpcode()) {
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unsigned Opc = N->getMachineOpcode();
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return Opc == M68k::ADJCALLSTACKDOWN || Opc == M68k::ADJCALLSTACKUP;
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}
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return false;
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}
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static CallSeqChainInfo getCallSeqChainInfo(SDValue Chain) {
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SmallVector<SDValue, 8> Worklist = {Chain};
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SmallPtrSet<SDNode *, 16> Visited;
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SDNode *Found = nullptr;
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while (!Worklist.empty()) {
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SDNode *CN = Worklist.pop_back_val().getNode();
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if (!CN || !Visited.insert(CN).second)
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continue;
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if (isCallSeqNode(CN)) {
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if (!Found)
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Found = CN;
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else if (Found != CN)
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return CallSeqChainInfo{nullptr, true};
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}
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if (CN->getOpcode() == ISD::TokenFactor) {
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for (const SDValue &Op : CN->op_values())
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if (Op.getValueType() == MVT::Other)
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Worklist.push_back(Op);
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continue;
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}
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for (const SDValue &Op : CN->op_values()) {
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if (Op.getValueType() == MVT::Other) {
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if (Worklist.size() == 8) {
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// We can't actually evaluate all branches,
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// be pessimistic and fail out.
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return CallSeqChainInfo{nullptr, true};
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}
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Worklist.push_back(Op);
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break;
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}
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}
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}
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return CallSeqChainInfo{Found, false};
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}
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// Helper for use in TableGen. We can't safely use a combined load/store in the
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// case where a token factor can cause a chain dep on a different call sequence.
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// Look for that case and return false if we can't confirm it's safe. This is
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// necessary due to the nesting level tracking in
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// ScheduleDAGRRList::FindCallSeqStart.
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static bool isSafeStoreLoad(SDNode *N) {
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auto *ST = dyn_cast<StoreSDNode>(N);
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if (!ST)
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return false;
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auto *LD = dyn_cast<LoadSDNode>(ST->getValue());
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if (!LD)
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return false;
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// Load and store chains can be unrelated; guard against either side
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// depending on a different call sequence boundary.
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CallSeqChainInfo LoadInfo = getCallSeqChainInfo(LD->getChain());
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CallSeqChainInfo StoreInfo = getCallSeqChainInfo(ST->getChain());
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if (LoadInfo.Multiple || StoreInfo.Multiple)
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return false;
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if (!LoadInfo.Node && !StoreInfo.Node)
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return true;
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return LoadInfo.Node && StoreInfo.Node && LoadInfo.Node == StoreInfo.Node;
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}
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class M68kDAGToDAGISel : public SelectionDAGISel {
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public:
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M68kDAGToDAGISel() = delete;
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explicit M68kDAGToDAGISel(M68kTargetMachine &TM)
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: SelectionDAGISel(TM), Subtarget(nullptr) {}
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bool runOnMachineFunction(MachineFunction &MF) override;
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bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
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private:
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/// Keep a pointer to the M68kSubtarget around so that we can
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/// make the right decision when generating code for different targets.
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const M68kSubtarget *Subtarget;
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// Include the pieces autogenerated from the target description.
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#include "M68kGenDAGISel.inc"
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/// getTargetMachine - Return a reference to the TargetMachine, casted
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/// to the target-specific type.
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const M68kTargetMachine &getTargetMachine() {
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return static_cast<const M68kTargetMachine &>(TM);
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}
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void Select(SDNode *N) override;
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// Insert instructions to initialize the global base register in the
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// first MBB of the function.
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// HMM... do i need this?
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void initGlobalBaseReg(MachineFunction &MF);
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bool foldOffsetIntoAddress(uint64_t Offset, M68kISelAddressMode &AM);
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bool matchLoadInAddress(LoadSDNode *N, M68kISelAddressMode &AM);
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bool matchAddress(SDValue N, M68kISelAddressMode &AM);
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bool matchAddressBase(SDValue N, M68kISelAddressMode &AM);
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bool matchAddressRecursively(SDValue N, M68kISelAddressMode &AM,
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unsigned Depth);
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bool matchADD(SDValue &N, M68kISelAddressMode &AM, unsigned Depth);
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bool matchWrapper(SDValue N, M68kISelAddressMode &AM);
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std::pair<bool, SDNode *> selectNode(SDNode *Node);
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bool SelectARI(SDNode *Parent, SDValue N, SDValue &Base);
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bool SelectARIPI(SDNode *Parent, SDValue N, SDValue &Base);
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bool SelectARIPD(SDNode *Parent, SDValue N, SDValue &Base);
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bool SelectARID(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Base);
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bool SelectARII(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Base,
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SDValue &Index);
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bool SelectAL(SDNode *Parent, SDValue N, SDValue &Sym);
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bool SelectPCD(SDNode *Parent, SDValue N, SDValue &Imm);
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bool SelectPCI(SDNode *Parent, SDValue N, SDValue &Imm, SDValue &Index);
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bool SelectInlineAsmMemoryOperand(const SDValue &Op,
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InlineAsm::ConstraintCode ConstraintID,
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std::vector<SDValue> &OutOps) override;
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// If Address Mode represents Frame Index store FI in Disp and
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// Displacement bit size in Base. These values are read symmetrically by
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// M68kRegisterInfo::eliminateFrameIndex method
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inline bool getFrameIndexAddress(M68kISelAddressMode &AM, const SDLoc &DL,
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SDValue &Disp, SDValue &Base) {
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if (AM.BaseType == M68kISelAddressMode::Base::FrameIndexBase) {
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Disp = getI32Imm(AM.Disp, DL);
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Base = CurDAG->getTargetFrameIndex(
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AM.BaseFrameIndex, TLI->getPointerTy(CurDAG->getDataLayout()));
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return true;
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}
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return false;
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}
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// Gets a symbol plus optional displacement
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inline bool getSymbolicDisplacement(M68kISelAddressMode &AM, const SDLoc &DL,
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SDValue &Sym) {
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if (AM.GV) {
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Sym = CurDAG->getTargetGlobalAddress(AM.GV, SDLoc(), MVT::i32, AM.Disp,
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AM.SymbolFlags);
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return true;
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}
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if (AM.CP) {
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Sym = CurDAG->getTargetConstantPool(AM.CP, MVT::i32, AM.Alignment,
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AM.Disp, AM.SymbolFlags);
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return true;
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}
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if (AM.ES) {
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assert(!AM.Disp && "Non-zero displacement is ignored with ES.");
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Sym = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i32, AM.SymbolFlags);
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return true;
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}
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if (AM.MCSym) {
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assert(!AM.Disp && "Non-zero displacement is ignored with MCSym.");
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assert(AM.SymbolFlags == 0 && "oo");
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Sym = CurDAG->getMCSymbol(AM.MCSym, MVT::i32);
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return true;
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}
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if (AM.JT != -1) {
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assert(!AM.Disp && "Non-zero displacement is ignored with JT.");
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Sym = CurDAG->getTargetJumpTable(AM.JT, MVT::i32, AM.SymbolFlags);
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return true;
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}
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if (AM.BlockAddr) {
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Sym = CurDAG->getTargetBlockAddress(AM.BlockAddr, MVT::i32, AM.Disp,
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AM.SymbolFlags);
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return true;
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}
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return false;
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}
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/// Return a target constant with the specified value of type i8.
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inline SDValue getI8Imm(int64_t Imm, const SDLoc &DL) {
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return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i8);
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}
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/// Return a target constant with the specified value of type i8.
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inline SDValue getI16Imm(int64_t Imm, const SDLoc &DL) {
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return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i16);
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}
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/// Return a target constant with the specified value, of type i32.
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inline SDValue getI32Imm(int64_t Imm, const SDLoc &DL) {
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return CurDAG->getSignedTargetConstant(Imm, DL, MVT::i32);
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}
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/// Return a reference to the TargetInstrInfo, casted to the target-specific
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/// type.
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const M68kInstrInfo *getInstrInfo() const {
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return Subtarget->getInstrInfo();
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}
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/// Return an SDNode that returns the value of the global base register.
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/// Output instructions required to initialize the global base register,
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/// if necessary.
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SDNode *getGlobalBaseReg();
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};
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class M68kDAGToDAGISelLegacy : public SelectionDAGISelLegacy {
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public:
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static char ID;
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explicit M68kDAGToDAGISelLegacy(M68kTargetMachine &TM)
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: SelectionDAGISelLegacy(ID, std::make_unique<M68kDAGToDAGISel>(TM)) {}
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};
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char M68kDAGToDAGISelLegacy::ID;
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} // namespace
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INITIALIZE_PASS(M68kDAGToDAGISelLegacy, DEBUG_TYPE, PASS_NAME, false, false)
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bool M68kDAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U,
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SDNode *Root) const {
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if (OptLevel == CodeGenOptLevel::None)
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return false;
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if (U == Root) {
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switch (U->getOpcode()) {
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default:
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return true;
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case M68kISD::SUB:
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case ISD::SUB:
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// Prefer NEG instruction when zero subtracts a value.
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// e.g.
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// move.l #0, %d0
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// sub.l (4,%sp), %d0
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// vs.
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// move.l (4,%sp), %d0
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// neg.l %d0
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if (llvm::isNullConstant(U->getOperand(0)))
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return false;
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break;
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}
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}
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return true;
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}
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bool M68kDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &MF.getSubtarget<M68kSubtarget>();
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return SelectionDAGISel::runOnMachineFunction(MF);
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}
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/// This pass converts a legalized DAG into a M68k-specific DAG,
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/// ready for instruction scheduling.
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FunctionPass *llvm::createM68kISelDag(M68kTargetMachine &TM) {
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return new M68kDAGToDAGISelLegacy(TM);
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}
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static bool doesDispFitFI(M68kISelAddressMode &AM) {
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if (!AM.isDispAddrType())
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return false;
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// -1 to make sure that resolved FI will fit into Disp field
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return isIntN(AM.getDispSize() - 1, AM.Disp);
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}
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static bool doesDispFit(M68kISelAddressMode &AM, int64_t Val) {
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if (!AM.isDispAddrType())
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return false;
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return isIntN(AM.getDispSize(), Val);
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}
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/// Return an SDNode that returns the value of the global base register.
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/// Output instructions required to initialize the global base register,
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/// if necessary.
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SDNode *M68kDAGToDAGISel::getGlobalBaseReg() {
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unsigned GlobalBaseReg = getInstrInfo()->getGlobalBaseReg(MF);
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auto &DL = MF->getDataLayout();
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return CurDAG->getRegister(GlobalBaseReg, TLI->getPointerTy(DL)).getNode();
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}
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bool M68kDAGToDAGISel::foldOffsetIntoAddress(uint64_t Offset,
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M68kISelAddressMode &AM) {
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// Cannot combine ExternalSymbol displacements with integer offsets.
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if (Offset != 0 && (AM.ES || AM.MCSym))
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return false;
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int64_t Val = AM.Disp + Offset;
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if (doesDispFit(AM, Val)) {
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AM.Disp = Val;
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Matchers
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
/// Helper for MatchAddress. Add the specified node to the
|
|
/// specified addressing mode without any further recursion.
|
|
bool M68kDAGToDAGISel::matchAddressBase(SDValue N, M68kISelAddressMode &AM) {
|
|
// Is the base register already occupied?
|
|
if (AM.hasBase()) {
|
|
// If so, check to see if the scale index register is set.
|
|
if (!AM.hasIndexReg()) {
|
|
AM.IndexReg = N;
|
|
AM.Scale = 1;
|
|
return true;
|
|
}
|
|
|
|
// Otherwise, we cannot select it.
|
|
return false;
|
|
}
|
|
|
|
// Default, generate it as a register.
|
|
AM.BaseType = M68kISelAddressMode::Base::RegBase;
|
|
AM.BaseReg = N;
|
|
return true;
|
|
}
|
|
|
|
/// TODO Add TLS support
|
|
bool M68kDAGToDAGISel::matchLoadInAddress(LoadSDNode *N,
|
|
M68kISelAddressMode &AM) {
|
|
return false;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::matchAddressRecursively(SDValue N,
|
|
M68kISelAddressMode &AM,
|
|
unsigned Depth) {
|
|
SDLoc DL(N);
|
|
|
|
// Limit recursion.
|
|
if (Depth > 5)
|
|
return matchAddressBase(N, AM);
|
|
|
|
// If this is already a %PC relative address, we can only merge immediates
|
|
// into it. Instead of handling this in every case, we handle it here.
|
|
// PC relative addressing: %PC + 16-bit displacement!
|
|
if (AM.isPCRelative()) {
|
|
// FIXME JumpTable and ExternalSymbol address currently don't like
|
|
// displacements. It isn't very important, but should be fixed for
|
|
// consistency.
|
|
|
|
if (ConstantSDNode *Cst = dyn_cast<ConstantSDNode>(N))
|
|
if (foldOffsetIntoAddress(Cst->getSExtValue(), AM))
|
|
return true;
|
|
return false;
|
|
}
|
|
|
|
switch (N.getOpcode()) {
|
|
default:
|
|
break;
|
|
|
|
case ISD::Constant: {
|
|
uint64_t Val = cast<ConstantSDNode>(N)->getSExtValue();
|
|
if (foldOffsetIntoAddress(Val, AM))
|
|
return true;
|
|
break;
|
|
}
|
|
|
|
case M68kISD::Wrapper:
|
|
case M68kISD::WrapperPC:
|
|
if (matchWrapper(N, AM))
|
|
return true;
|
|
break;
|
|
|
|
case ISD::LOAD:
|
|
if (matchLoadInAddress(cast<LoadSDNode>(N), AM))
|
|
return true;
|
|
break;
|
|
|
|
case ISD::OR:
|
|
// We want to look through a transform in InstCombine and DAGCombiner that
|
|
// turns 'add' into 'or', so we can treat this 'or' exactly like an 'add'.
|
|
// Example: (or (and x, 1), (shl y, 3)) --> (add (and x, 1), (shl y, 3))
|
|
// An 'lea' can then be used to match the shift (multiply) and add:
|
|
// and $1, %esi
|
|
// lea (%rsi, %rdi, 8), %rax
|
|
if (CurDAG->haveNoCommonBitsSet(N.getOperand(0), N.getOperand(1)) &&
|
|
matchADD(N, AM, Depth))
|
|
return true;
|
|
break;
|
|
|
|
case ISD::ADD:
|
|
if (matchADD(N, AM, Depth))
|
|
return true;
|
|
break;
|
|
|
|
case ISD::FrameIndex:
|
|
if (AM.isDispAddrType() &&
|
|
AM.BaseType == M68kISelAddressMode::Base::RegBase &&
|
|
AM.BaseReg.getNode() == nullptr && doesDispFitFI(AM)) {
|
|
AM.BaseType = M68kISelAddressMode::Base::FrameIndexBase;
|
|
AM.BaseFrameIndex = cast<FrameIndexSDNode>(N)->getIndex();
|
|
return true;
|
|
}
|
|
break;
|
|
|
|
case ISD::TargetGlobalTLSAddress: {
|
|
GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(N);
|
|
AM.GV = GA->getGlobal();
|
|
AM.SymbolFlags = GA->getTargetFlags();
|
|
return true;
|
|
}
|
|
}
|
|
|
|
return matchAddressBase(N, AM);
|
|
}
|
|
|
|
/// Add the specified node to the specified addressing mode, returning true if
|
|
/// it cannot be done. This just pattern matches for the addressing mode.
|
|
bool M68kDAGToDAGISel::matchAddress(SDValue N, M68kISelAddressMode &AM) {
|
|
// TODO: Post-processing: Convert lea(,%reg,2) to lea(%reg,%reg), which has
|
|
// a smaller encoding and avoids a scaled-index.
|
|
// And make sure it is an indexed mode
|
|
|
|
// TODO: Post-processing: Convert foo to foo(%pc), even in non-PIC mode,
|
|
// because it has a smaller encoding.
|
|
// Make sure this must be done only if PC* modes are currently being matched
|
|
return matchAddressRecursively(N, AM, 0);
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::matchADD(SDValue &N, M68kISelAddressMode &AM,
|
|
unsigned Depth) {
|
|
// Add an artificial use to this node so that we can keep track of
|
|
// it if it gets CSE'd with a different node.
|
|
HandleSDNode Handle(N);
|
|
|
|
M68kISelAddressMode Backup = AM;
|
|
if (matchAddressRecursively(N.getOperand(0), AM, Depth + 1) &&
|
|
matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth + 1)) {
|
|
return true;
|
|
}
|
|
AM = Backup;
|
|
|
|
// Try again after commuting the operands.
|
|
if (matchAddressRecursively(Handle.getValue().getOperand(1), AM, Depth + 1) &&
|
|
matchAddressRecursively(Handle.getValue().getOperand(0), AM, Depth + 1)) {
|
|
return true;
|
|
}
|
|
AM = Backup;
|
|
|
|
// If we couldn't fold both operands into the address at the same time,
|
|
// see if we can just put each operand into a register and fold at least
|
|
// the add.
|
|
if (!AM.hasBase() && !AM.hasIndexReg()) {
|
|
N = Handle.getValue();
|
|
AM.BaseReg = N.getOperand(0);
|
|
AM.IndexReg = N.getOperand(1);
|
|
AM.Scale = 1;
|
|
return true;
|
|
}
|
|
|
|
N = Handle.getValue();
|
|
return false;
|
|
}
|
|
|
|
/// Try to match M68kISD::Wrapper and M68kISD::WrapperPC nodes into an
|
|
/// addressing mode. These wrap things that will resolve down into a symbol
|
|
/// reference. If no match is possible, this returns true, otherwise it returns
|
|
/// false.
|
|
bool M68kDAGToDAGISel::matchWrapper(SDValue N, M68kISelAddressMode &AM) {
|
|
// If the addressing mode already has a symbol as the displacement, we can
|
|
// never match another symbol.
|
|
if (AM.hasSymbolicDisplacement())
|
|
return false;
|
|
|
|
SDValue N0 = N.getOperand(0);
|
|
|
|
if (N.getOpcode() == M68kISD::WrapperPC) {
|
|
|
|
// If cannot match here just restore the old version
|
|
M68kISelAddressMode Backup = AM;
|
|
|
|
if (AM.hasBase()) {
|
|
return false;
|
|
}
|
|
|
|
if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
AM.GV = G->getGlobal();
|
|
AM.SymbolFlags = G->getTargetFlags();
|
|
if (!foldOffsetIntoAddress(G->getOffset(), AM)) {
|
|
AM = Backup;
|
|
return false;
|
|
}
|
|
} else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
|
AM.CP = CP->getConstVal();
|
|
AM.Alignment = CP->getAlign();
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
|
if (!foldOffsetIntoAddress(CP->getOffset(), AM)) {
|
|
AM = Backup;
|
|
return false;
|
|
}
|
|
} else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
AM.ES = S->getSymbol();
|
|
AM.SymbolFlags = S->getTargetFlags();
|
|
} else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
|
|
AM.MCSym = S->getMCSymbol();
|
|
} else if (auto *J = dyn_cast<JumpTableSDNode>(N0)) {
|
|
AM.JT = J->getIndex();
|
|
AM.SymbolFlags = J->getTargetFlags();
|
|
} else if (auto *BA = dyn_cast<BlockAddressSDNode>(N0)) {
|
|
AM.BlockAddr = BA->getBlockAddress();
|
|
AM.SymbolFlags = BA->getTargetFlags();
|
|
if (!foldOffsetIntoAddress(BA->getOffset(), AM)) {
|
|
AM = Backup;
|
|
return false;
|
|
}
|
|
} else
|
|
llvm_unreachable("Unhandled symbol reference node.");
|
|
|
|
AM.setBaseReg(CurDAG->getRegister(M68k::PC, MVT::i32));
|
|
return true;
|
|
}
|
|
|
|
// This wrapper requires 32bit disp/imm field for Medium CM
|
|
if (!AM.isDisp32()) {
|
|
return false;
|
|
}
|
|
|
|
if (N.getOpcode() == M68kISD::Wrapper) {
|
|
if (auto *G = dyn_cast<GlobalAddressSDNode>(N0)) {
|
|
AM.GV = G->getGlobal();
|
|
AM.Disp += G->getOffset();
|
|
AM.SymbolFlags = G->getTargetFlags();
|
|
} else if (auto *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
|
|
AM.CP = CP->getConstVal();
|
|
AM.Alignment = CP->getAlign();
|
|
AM.Disp += CP->getOffset();
|
|
AM.SymbolFlags = CP->getTargetFlags();
|
|
} else if (auto *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
|
|
AM.ES = S->getSymbol();
|
|
AM.SymbolFlags = S->getTargetFlags();
|
|
} else if (auto *S = dyn_cast<MCSymbolSDNode>(N0)) {
|
|
AM.MCSym = S->getMCSymbol();
|
|
} else if (auto *J = dyn_cast<JumpTableSDNode>(N0)) {
|
|
AM.JT = J->getIndex();
|
|
AM.SymbolFlags = J->getTargetFlags();
|
|
} else if (auto *BA = dyn_cast<BlockAddressSDNode>(N0)) {
|
|
AM.BlockAddr = BA->getBlockAddress();
|
|
AM.Disp += BA->getOffset();
|
|
AM.SymbolFlags = BA->getTargetFlags();
|
|
} else
|
|
llvm_unreachable("Unhandled symbol reference node.");
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Selectors
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
void M68kDAGToDAGISel::Select(SDNode *Node) {
|
|
unsigned Opcode = Node->getOpcode();
|
|
SDLoc DL(Node);
|
|
|
|
LLVM_DEBUG(dbgs() << "Selecting: "; Node->dump(CurDAG); dbgs() << '\n');
|
|
|
|
if (Node->isMachineOpcode()) {
|
|
LLVM_DEBUG(dbgs() << "== "; Node->dump(CurDAG); dbgs() << '\n');
|
|
Node->setNodeId(-1);
|
|
return; // Already selected.
|
|
}
|
|
|
|
switch (Opcode) {
|
|
default:
|
|
break;
|
|
|
|
case ISD::GLOBAL_OFFSET_TABLE: {
|
|
SDValue GOT = CurDAG->getTargetExternalSymbol(
|
|
"_GLOBAL_OFFSET_TABLE_", MVT::i32, M68kII::MO_GOTPCREL);
|
|
MachineSDNode *Res =
|
|
CurDAG->getMachineNode(M68k::LEA32q, DL, MVT::i32, GOT);
|
|
ReplaceNode(Node, Res);
|
|
return;
|
|
}
|
|
|
|
case M68kISD::GLOBAL_BASE_REG:
|
|
ReplaceNode(Node, getGlobalBaseReg());
|
|
return;
|
|
}
|
|
|
|
SelectCode(Node);
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectARIPI(SDNode *Parent, SDValue N, SDValue &Base) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARIPI: ");
|
|
LLVM_DEBUG(dbgs() << "NOT IMPLEMENTED\n");
|
|
return false;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectARIPD(SDNode *Parent, SDValue N, SDValue &Base) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARIPD: ");
|
|
LLVM_DEBUG(dbgs() << "NOT IMPLEMENTED\n");
|
|
return false;
|
|
}
|
|
|
|
[[maybe_unused]] static bool allowARIDWithDisp(SDNode *Parent) {
|
|
if (!Parent)
|
|
return false;
|
|
switch (Parent->getOpcode()) {
|
|
case ISD::LOAD:
|
|
case ISD::STORE:
|
|
case ISD::ATOMIC_LOAD:
|
|
case ISD::ATOMIC_STORE:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectARID(SDNode *Parent, SDValue N, SDValue &Disp,
|
|
SDValue &Base) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARID: ");
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::ARID);
|
|
|
|
if (!matchAddress(N, AM))
|
|
return false;
|
|
|
|
if (AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match PC relative address\n");
|
|
return false;
|
|
}
|
|
|
|
// If this is a frame index, grab it
|
|
if (getFrameIndexAddress(AM, SDLoc(N), Disp, Base)) {
|
|
LLVM_DEBUG(dbgs() << "SUCCESS matched FI\n");
|
|
return true;
|
|
}
|
|
|
|
if (AM.hasIndexReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Index\n");
|
|
return false;
|
|
}
|
|
|
|
if (!AM.hasBaseReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: No Base reg\n");
|
|
return false;
|
|
}
|
|
|
|
Base = AM.BaseReg;
|
|
|
|
if (getSymbolicDisplacement(AM, SDLoc(N), Disp)) {
|
|
assert((!AM.Disp || allowARIDWithDisp(Parent)) &&
|
|
"Should not be any displacement");
|
|
LLVM_DEBUG(dbgs() << "SUCCESS, matched Symbol\n");
|
|
return true;
|
|
}
|
|
|
|
// Give a chance to AddrType::ARI
|
|
if (AM.Disp == 0) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: No displacement\n");
|
|
return false;
|
|
}
|
|
|
|
Disp = getI16Imm(AM.Disp, SDLoc(N));
|
|
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
static bool isAddressBase(const SDValue &N) {
|
|
switch (N.getOpcode()) {
|
|
case ISD::ADD:
|
|
case ISD::ADDC:
|
|
return llvm::any_of(N.getNode()->ops(),
|
|
[](const SDUse &U) { return isAddressBase(U.get()); });
|
|
case M68kISD::Wrapper:
|
|
case M68kISD::WrapperPC:
|
|
case M68kISD::GLOBAL_BASE_REG:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool AllowARIIWithZeroDisp(SDNode *Parent) {
|
|
if (!Parent)
|
|
return false;
|
|
switch (Parent->getOpcode()) {
|
|
case ISD::LOAD:
|
|
case ISD::STORE:
|
|
case ISD::ATOMIC_LOAD:
|
|
case ISD::ATOMIC_STORE:
|
|
case ISD::ATOMIC_CMP_SWAP:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectARII(SDNode *Parent, SDValue N, SDValue &Disp,
|
|
SDValue &Base, SDValue &Index) {
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::ARII);
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARII: ");
|
|
|
|
if (!matchAddress(N, AM))
|
|
return false;
|
|
|
|
if (AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: PC relative\n");
|
|
return false;
|
|
}
|
|
|
|
if (!AM.hasIndexReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: No Index\n");
|
|
return false;
|
|
}
|
|
|
|
if (!AM.hasBaseReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: No Base\n");
|
|
return false;
|
|
}
|
|
|
|
if (!isAddressBase(AM.BaseReg) && isAddressBase(AM.IndexReg)) {
|
|
Base = AM.IndexReg;
|
|
Index = AM.BaseReg;
|
|
} else {
|
|
Base = AM.BaseReg;
|
|
Index = AM.IndexReg;
|
|
}
|
|
|
|
if (AM.hasSymbolicDisplacement()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT, Cannot match symbolic displacement\n");
|
|
return false;
|
|
}
|
|
|
|
// The idea here is that we want to use AddrType::ARII without displacement
|
|
// only if necessary like memory operations, otherwise this must be lowered
|
|
// into addition
|
|
if (AM.Disp == 0 && !AllowARIIWithZeroDisp(Parent)) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Displacement is Zero\n");
|
|
return false;
|
|
}
|
|
|
|
Disp = getI8Imm(AM.Disp, SDLoc(N));
|
|
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectAL(SDNode *Parent, SDValue N, SDValue &Sym) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::AL: ");
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::AL);
|
|
|
|
if (!matchAddress(N, AM)) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Match failed\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match PC relative address\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.hasBase()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Base\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.hasIndexReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Index\n");
|
|
return false;
|
|
}
|
|
|
|
if (getSymbolicDisplacement(AM, SDLoc(N), Sym)) {
|
|
LLVM_DEBUG(dbgs() << "SUCCESS: Matched symbol\n");
|
|
return true;
|
|
}
|
|
|
|
if (AM.Disp) {
|
|
Sym = getI32Imm(AM.Disp, SDLoc(N));
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
LLVM_DEBUG(dbgs() << "REJECT: Not Symbol or Disp\n");
|
|
return false;
|
|
;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectPCD(SDNode *Parent, SDValue N, SDValue &Disp) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::PCD: ");
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::PCD);
|
|
|
|
if (!matchAddress(N, AM))
|
|
return false;
|
|
|
|
if (!AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Not PC relative\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.hasIndexReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Index\n");
|
|
return false;
|
|
}
|
|
|
|
if (getSymbolicDisplacement(AM, SDLoc(N), Disp)) {
|
|
LLVM_DEBUG(dbgs() << "SUCCESS, matched Symbol\n");
|
|
return true;
|
|
}
|
|
|
|
Disp = getI16Imm(AM.Disp, SDLoc(N));
|
|
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectPCI(SDNode *Parent, SDValue N, SDValue &Disp,
|
|
SDValue &Index) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::PCI: ");
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::PCI);
|
|
|
|
if (!matchAddress(N, AM))
|
|
return false;
|
|
|
|
if (!AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Not PC relative\n");
|
|
return false;
|
|
}
|
|
|
|
if (!AM.hasIndexReg()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: No Index\n");
|
|
return false;
|
|
}
|
|
|
|
Index = AM.IndexReg;
|
|
|
|
if (getSymbolicDisplacement(AM, SDLoc(N), Disp)) {
|
|
assert(!AM.Disp && "Should not be any displacement");
|
|
LLVM_DEBUG(dbgs() << "SUCCESS, matched Symbol\n");
|
|
return true;
|
|
}
|
|
|
|
Disp = getI8Imm(AM.Disp, SDLoc(N));
|
|
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectARI(SDNode *Parent, SDValue N, SDValue &Base) {
|
|
LLVM_DEBUG(dbgs() << "Selecting AddrType::ARI: ");
|
|
M68kISelAddressMode AM(M68kISelAddressMode::AddrType::ARI);
|
|
|
|
if (!matchAddress(N, AM)) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Match failed\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.isPCRelative()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match PC relative address\n");
|
|
return false;
|
|
}
|
|
|
|
// AddrType::ARI does not use these
|
|
if (AM.hasIndexReg() || AM.Disp != 0) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Index or Disp\n");
|
|
return false;
|
|
}
|
|
|
|
// Must be matched by AddrType::AL
|
|
if (AM.hasSymbolicDisplacement()) {
|
|
LLVM_DEBUG(dbgs() << "REJECT: Cannot match Symbolic Disp\n");
|
|
return false;
|
|
}
|
|
|
|
if (AM.hasBaseReg()) {
|
|
Base = AM.BaseReg;
|
|
LLVM_DEBUG(dbgs() << "SUCCESS\n");
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
bool M68kDAGToDAGISel::SelectInlineAsmMemoryOperand(
|
|
const SDValue &Op, InlineAsm::ConstraintCode ConstraintID,
|
|
std::vector<SDValue> &OutOps) {
|
|
// In order to tell AsmPrinter the exact addressing mode we select here, which
|
|
// might comprise of multiple SDValues (hence MachineOperands), a 32-bit
|
|
// immediate value is prepended to the list of selected SDValues to indicate
|
|
// the addressing mode kind.
|
|
using AMK = M68k::MemAddrModeKind;
|
|
auto addKind = [this](SDValue &Opnd, AMK Kind) -> bool {
|
|
Opnd = CurDAG->getTargetConstant(unsigned(Kind), SDLoc(), MVT::i32);
|
|
return true;
|
|
};
|
|
|
|
switch (ConstraintID) {
|
|
// Generic memory operand.
|
|
case InlineAsm::ConstraintCode::m: {
|
|
// Try every supported (memory) addressing modes.
|
|
SDValue Operands[4];
|
|
|
|
// TODO: The ordering of the following SelectXXX is relatively...arbitrary,
|
|
// right now we simply sort them by descending complexity. Maybe we should
|
|
// adjust this by code model and/or relocation mode in the future.
|
|
if (SelectARII(nullptr, Op, Operands[1], Operands[2], Operands[3]) &&
|
|
addKind(Operands[0], AMK::f)) {
|
|
OutOps.insert(OutOps.end(), &Operands[0], Operands + 4);
|
|
return false;
|
|
}
|
|
|
|
if ((SelectPCI(nullptr, Op, Operands[1], Operands[2]) &&
|
|
addKind(Operands[0], AMK::k)) ||
|
|
(SelectARID(nullptr, Op, Operands[1], Operands[2]) &&
|
|
addKind(Operands[0], AMK::p))) {
|
|
OutOps.insert(OutOps.end(), &Operands[0], Operands + 3);
|
|
return false;
|
|
}
|
|
|
|
if ((SelectPCD(nullptr, Op, Operands[1]) && addKind(Operands[0], AMK::q)) ||
|
|
(SelectARI(nullptr, Op, Operands[1]) && addKind(Operands[0], AMK::j)) ||
|
|
(SelectAL(nullptr, Op, Operands[1]) && addKind(Operands[0], AMK::b))) {
|
|
OutOps.insert(OutOps.end(), {Operands[0], Operands[1]});
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
// 'Q': Address register indirect addressing.
|
|
case InlineAsm::ConstraintCode::Q: {
|
|
SDValue AMKind, Base;
|
|
// 'j' addressing mode.
|
|
// TODO: Add support for 'o' and 'e' after their
|
|
// select functions are implemented.
|
|
if (SelectARI(nullptr, Op, Base) && addKind(AMKind, AMK::j)) {
|
|
OutOps.insert(OutOps.end(), {AMKind, Base});
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
// 'U': Address register indirect w/ constant offset addressing.
|
|
case InlineAsm::ConstraintCode::Um: {
|
|
SDValue AMKind, Base, Offset;
|
|
// 'p' addressing mode.
|
|
if (SelectARID(nullptr, Op, Offset, Base) && addKind(AMKind, AMK::p)) {
|
|
OutOps.insert(OutOps.end(), {AMKind, Offset, Base});
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
default:
|
|
return true;
|
|
}
|
|
}
|