bd4784a913
SpacemiT X100 is a 4-issue, out-of-order, RVA23 processor. This patch introduces the base scheduling model for scalar instructions. The scheduling model for RVV will be added in a future update.
371 lines
13 KiB
TableGen
371 lines
13 KiB
TableGen
//- RISCVSchedSpacemitX100.td - Spacemit X100 Scheduling Defs -*- tablegen -*-//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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//
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// Scheduler model for the SpacemiT-X100 processor.
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//
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//===----------------------------------------------------------------------===//
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def SpacemitX100Model : SchedMachineModel {
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let IssueWidth = 4; // 4 micro-ops are dispatched per cycle.
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let MicroOpBufferSize = 192; // Max micro-ops that can be buffered.
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// 64 entry ROB. Max 3 micro-ops share one entry.
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let LoadLatency = 3; // Cycles for loads to access the cache.
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let MispredictPenalty = 9; // Extra cycles for a mispredicted branch.
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let CompleteModel = 0;
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let UnsupportedFeatures = [HasStdExtZknd, HasStdExtZkne, HasStdExtZknh,
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HasStdExtZksed, HasStdExtZksh, HasStdExtZkr,
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HasVInstructions];
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}
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let SchedModel = SpacemitX100Model in {
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//===----------------------------------------------------------------------===//
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// Define processor resources for Spacemit-X100
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let BufferSize = 6 in {
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// IQ0, IQ1, BQ: 12 entry queue, can accept 2 ops and issue 1 op per cycle
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// To model the accept bandwidth, split into 2 sub-queues of 6 entry each
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def SMTX100_IQ0 : ProcResource<2>; //Integer Queue 0
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def SMTX100_IQ1 : ProcResource<2>; //Integer Queue 1
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def SMTX100_BQ : ProcResource<2>; //Branch Queue
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}
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let BufferSize = 4 in {
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// LSQ: 16 entry queue, can accept 4 ops and issue 2 op per cycle
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// To model the accept bandwidth, split into 4 sub-queues of 4 entry each
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def SMTX100_LSQ : ProcResource<4>; //Load Store Queue
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// FQ0, FQ1: 8 entry queue, can accept 2 ops and issue 1 op per cycle
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// To model the accept bandwidth, split into 2 sub-queues of 4 entry each
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def SMTX100_FQ0 : ProcResource<2>; //Float Queue 0
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def SMTX100_FQ1 : ProcResource<2>; //Float Queue 1
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}
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def SMTX100_IQ : ProcResGroup<[SMTX100_IQ0, SMTX100_IQ1]>;
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def SMTX100_FQ : ProcResGroup<[SMTX100_FQ0, SMTX100_FQ1]>;
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//===----------------------------------------------------------------------===//
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// Branching
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let Latency = 2 in {
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def : WriteRes<WriteJmp, [SMTX100_BQ]>;
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def : WriteRes<WriteJal, [SMTX100_BQ]>;
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def : WriteRes<WriteJalr, [SMTX100_BQ]>;
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}
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// Integer arithmetic and logic
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def : WriteRes<WriteIALU32, [SMTX100_IQ]>;
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def : WriteRes<WriteIALU, [SMTX100_IQ]>;
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def : WriteRes<WriteShiftImm32, [SMTX100_IQ]>;
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def : WriteRes<WriteShiftImm, [SMTX100_IQ]>;
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def : WriteRes<WriteShiftReg32, [SMTX100_IQ]>;
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def : WriteRes<WriteShiftReg, [SMTX100_IQ]>;
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// Integer multiplication
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def : WriteRes<WriteIMul32, [SMTX100_IQ1]> { let Latency = 2; }
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def : WriteRes<WriteIMul, [SMTX100_IQ1]> { let Latency = 3; }
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// Integer division/remainder
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// Latency is 4-14, Worst case latency is used
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let Latency = 14, ReleaseAtCycles = [14] in {
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def : WriteRes<WriteIDiv32, [SMTX100_IQ0]>;
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def : WriteRes<WriteIRem32, [SMTX100_IQ0]>;
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}
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// Latency is 4-22, Worst case latency is used
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let Latency = 22, ReleaseAtCycles = [22] in {
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def : WriteRes<WriteIDiv, [SMTX100_IQ0]>;
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def : WriteRes<WriteIRem, [SMTX100_IQ0]>;
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}
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// Bitmanip
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def : WriteRes<WriteRotateImm, [SMTX100_IQ]>;
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def : WriteRes<WriteRotateImm32, [SMTX100_IQ]>;
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def : WriteRes<WriteRotateReg, [SMTX100_IQ]>;
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def : WriteRes<WriteRotateReg32, [SMTX100_IQ]>;
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def : WriteRes<WriteCLZ, [SMTX100_IQ]>;
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def : WriteRes<WriteCLZ32, [SMTX100_IQ]>;
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def : WriteRes<WriteCTZ, [SMTX100_IQ]>;
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def : WriteRes<WriteCTZ32, [SMTX100_IQ]>;
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let Latency = 2 in {
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def : WriteRes<WriteCPOP, [SMTX100_IQ]>;
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def : WriteRes<WriteCPOP32, [SMTX100_IQ]>;
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}
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def : WriteRes<WriteORCB, [SMTX100_IQ]>;
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def : WriteRes<WriteIMinMax, [SMTX100_IQ]>;
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def : WriteRes<WriteREV8, [SMTX100_IQ]>;
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def : WriteRes<WriteSHXADD, [SMTX100_IQ]>;
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def : WriteRes<WriteSHXADD32, [SMTX100_IQ]>;
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def : WriteRes<WriteCLMUL, [SMTX100_IQ]> { let Latency = 2; }
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// Single-bit instructions
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def : WriteRes<WriteSingleBit, [SMTX100_IQ]>;
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def : WriteRes<WriteSingleBitImm, [SMTX100_IQ]>;
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def : WriteRes<WriteBEXT, [SMTX100_IQ]>;
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def : WriteRes<WriteBEXTI, [SMTX100_IQ]>;
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// Memory/Atomic memory
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def : WriteRes<WriteSTB, [SMTX100_LSQ]>;
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def : WriteRes<WriteSTH, [SMTX100_LSQ]>;
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def : WriteRes<WriteSTW, [SMTX100_LSQ]>;
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def : WriteRes<WriteSTD, [SMTX100_LSQ]>;
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def : WriteRes<WriteFST16, [SMTX100_LSQ]>;
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def : WriteRes<WriteFST32, [SMTX100_LSQ]>;
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def : WriteRes<WriteFST64, [SMTX100_LSQ]>;
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let Latency = 3 in {
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def : WriteRes<WriteLDB, [SMTX100_LSQ]>;
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def : WriteRes<WriteLDH, [SMTX100_LSQ]>;
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def : WriteRes<WriteLDW, [SMTX100_LSQ]>;
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def : WriteRes<WriteLDD, [SMTX100_LSQ]>;
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}
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let Latency = 4 in {
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def : WriteRes<WriteFLD16, [SMTX100_LSQ]>;
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def : WriteRes<WriteFLD32, [SMTX100_LSQ]>;
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def : WriteRes<WriteFLD64, [SMTX100_LSQ]>;
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}
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// Atomics
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// Latency is at least 7, not sure worst case latency now
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let Latency = 7 in {
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def : WriteRes<WriteAtomicSTW, [SMTX100_LSQ]>;
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def : WriteRes<WriteAtomicSTD, [SMTX100_LSQ]>;
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def : WriteRes<WriteAtomicLDW, [SMTX100_LSQ]>;
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def : WriteRes<WriteAtomicLDD, [SMTX100_LSQ]>;
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def : WriteRes<WriteAtomicW, [SMTX100_LSQ]>;
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def : WriteRes<WriteAtomicD, [SMTX100_LSQ]>;
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}
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// Floating point units Half precision
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let Latency = 3 in {
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def : WriteRes<WriteFAdd16, [SMTX100_FQ]>;
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def : WriteRes<WriteFMul16, [SMTX100_FQ]>;
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def : WriteRes<WriteFSGNJ16, [SMTX100_FQ]>;
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def : WriteRes<WriteFMinMax16, [SMTX100_FQ]>;
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}
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def : WriteRes<WriteFMA16, [SMTX100_FQ]> { let Latency = 5; }
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// Latency is 4-12, Worst case latency is used
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let Latency = 12, ReleaseAtCycles = [12] in {
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def : WriteRes<WriteFDiv16, [SMTX100_FQ0]>;
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def : WriteRes<WriteFSqrt16, [SMTX100_FQ0]>;
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}
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// Single precision
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let Latency = 3 in {
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def : WriteRes<WriteFAdd32, [SMTX100_FQ]>;
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def : WriteRes<WriteFSGNJ32, [SMTX100_FQ]>;
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def : WriteRes<WriteFMinMax32, [SMTX100_FQ]>;
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}
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def : WriteRes<WriteFMul32, [SMTX100_FQ]> { let Latency = 4; }
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def : WriteRes<WriteFMA32, [SMTX100_FQ]> { let Latency = 5; }
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// Latency is 4-12, Worst case latency is used
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let Latency = 12, ReleaseAtCycles = [12] in {
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def : WriteRes<WriteFDiv32, [SMTX100_FQ0]>;
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def : WriteRes<WriteFSqrt32, [SMTX100_FQ0]>;
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}
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// Double precision
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let Latency = 3 in {
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def : WriteRes<WriteFAdd64, [SMTX100_FQ]>;
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def : WriteRes<WriteFSGNJ64, [SMTX100_FQ]>;
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def : WriteRes<WriteFMinMax64, [SMTX100_FQ]>;
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}
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def : WriteRes<WriteFMul64, [SMTX100_FQ]> { let Latency = 4; }
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def : WriteRes<WriteFMA64, [SMTX100_FQ]> { let Latency = 4; }
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// Latency is 4-20, Worst case latency is used
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let Latency = 20, ReleaseAtCycles = [20] in {
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def : WriteRes<WriteFDiv64, [SMTX100_FQ0]>;
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def : WriteRes<WriteFSqrt64, [SMTX100_FQ0]>;
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}
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// Zfa
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let Latency = 3 in {
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def : WriteRes<WriteFRoundF16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFRoundF32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFRoundF64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFLI16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFLI32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFLI64, [SMTX100_FQ1]>;
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}
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// Conversions
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let Latency = 3 in {
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def : WriteRes<WriteFCvtF16ToI32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF32ToI32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF32ToI64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF64ToI64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF64ToI32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF16ToI64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI32ToF16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI32ToF32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI32ToF64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI64ToF16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI64ToF32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtI64ToF64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF16ToF32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF16ToF64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF32ToF16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF32ToF64, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF64ToF16, [SMTX100_FQ1]>;
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def : WriteRes<WriteFCvtF64ToF32, [SMTX100_FQ1]>;
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def : WriteRes<WriteFClass16, [SMTX100_FQ]>;
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def : WriteRes<WriteFClass32, [SMTX100_FQ]>;
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def : WriteRes<WriteFClass64, [SMTX100_FQ]>;
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def : WriteRes<WriteFCmp16, [SMTX100_FQ]>;
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def : WriteRes<WriteFCmp32, [SMTX100_FQ]>;
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def : WriteRes<WriteFCmp64, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovF16ToI16, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovI16ToF16, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovF32ToI32, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovI32ToF32, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovF64ToI64, [SMTX100_FQ]>;
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def : WriteRes<WriteFMovI64ToF64, [SMTX100_FQ]>;
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}
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// Others
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def : WriteRes<WriteCSR, [SMTX100_IQ0]>;
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def : WriteRes<WriteNop, [SMTX100_IQ]>;
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//===----------------------------------------------------------------------===//
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// Bypass and advance
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def : ReadAdvance<ReadJmp, 0>;
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def : ReadAdvance<ReadJalr, 0>;
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def : ReadAdvance<ReadCSR, 0>;
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def : ReadAdvance<ReadStoreData, 0>;
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def : ReadAdvance<ReadMemBase, 0>;
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def : ReadAdvance<ReadIALU, 0>;
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def : ReadAdvance<ReadIALU32, 0>;
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def : ReadAdvance<ReadShiftImm, 0>;
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def : ReadAdvance<ReadShiftImm32, 0>;
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def : ReadAdvance<ReadShiftReg, 0>;
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def : ReadAdvance<ReadShiftReg32, 0>;
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def : ReadAdvance<ReadIDiv, 0>;
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def : ReadAdvance<ReadIDiv32, 0>;
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def : ReadAdvance<ReadIRem, 0>;
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def : ReadAdvance<ReadIRem32, 0>;
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def : ReadAdvance<ReadIMul, 0>;
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def : ReadAdvance<ReadIMul32, 0>;
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def : ReadAdvance<ReadAtomicWA, 0>;
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def : ReadAdvance<ReadAtomicWD, 0>;
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def : ReadAdvance<ReadAtomicDA, 0>;
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def : ReadAdvance<ReadAtomicDD, 0>;
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def : ReadAdvance<ReadAtomicLDW, 0>;
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def : ReadAdvance<ReadAtomicLDD, 0>;
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def : ReadAdvance<ReadAtomicSTW, 0>;
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def : ReadAdvance<ReadAtomicSTD, 0>;
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def : ReadAdvance<ReadFStoreData, 0>;
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def : ReadAdvance<ReadFMemBase, 0>;
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def : ReadAdvance<ReadFAdd16, 0>;
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def : ReadAdvance<ReadFAdd32, 0>;
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def : ReadAdvance<ReadFAdd64, 0>;
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def : ReadAdvance<ReadFMul16, 0>;
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def : ReadAdvance<ReadFMA16, 0>;
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def : ReadAdvance<ReadFMA16Addend, 0>;
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def : ReadAdvance<ReadFMul32, 0>;
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def : ReadAdvance<ReadFMul64, 0>;
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def : ReadAdvance<ReadFMA32, 0>;
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def : ReadAdvance<ReadFMA32Addend, 0>;
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def : ReadAdvance<ReadFMA64, 0>;
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def : ReadAdvance<ReadFMA64Addend, 0>;
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def : ReadAdvance<ReadFDiv16, 0>;
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def : ReadAdvance<ReadFDiv32, 0>;
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def : ReadAdvance<ReadFDiv64, 0>;
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def : ReadAdvance<ReadFSqrt16, 0>;
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def : ReadAdvance<ReadFSqrt32, 0>;
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def : ReadAdvance<ReadFSqrt64, 0>;
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def : ReadAdvance<ReadFCmp16, 0>;
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def : ReadAdvance<ReadFCmp32, 0>;
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def : ReadAdvance<ReadFCmp64, 0>;
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def : ReadAdvance<ReadFSGNJ16, 0>;
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def : ReadAdvance<ReadFSGNJ32, 0>;
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def : ReadAdvance<ReadFSGNJ64, 0>;
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def : ReadAdvance<ReadFMinMax16, 0>;
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def : ReadAdvance<ReadFMinMax32, 0>;
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def : ReadAdvance<ReadFMinMax64, 0>;
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def : ReadAdvance<ReadFCvtF16ToI32, 0>;
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def : ReadAdvance<ReadFCvtF16ToI64, 0>;
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def : ReadAdvance<ReadFCvtF32ToI32, 0>;
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def : ReadAdvance<ReadFCvtF32ToI64, 0>;
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def : ReadAdvance<ReadFCvtF64ToI32, 0>;
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def : ReadAdvance<ReadFCvtF64ToI64, 0>;
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def : ReadAdvance<ReadFCvtI32ToF16, 0>;
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def : ReadAdvance<ReadFCvtI32ToF32, 0>;
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def : ReadAdvance<ReadFCvtI32ToF64, 0>;
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def : ReadAdvance<ReadFCvtI64ToF16, 0>;
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def : ReadAdvance<ReadFCvtI64ToF32, 0>;
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def : ReadAdvance<ReadFCvtI64ToF64, 0>;
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def : ReadAdvance<ReadFCvtF32ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF32, 0>;
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def : ReadAdvance<ReadFCvtF16ToF32, 0>;
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def : ReadAdvance<ReadFCvtF32ToF16, 0>;
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def : ReadAdvance<ReadFCvtF16ToF64, 0>;
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def : ReadAdvance<ReadFCvtF64ToF16, 0>;
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def : ReadAdvance<ReadFMovF16ToI16, 0>;
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def : ReadAdvance<ReadFMovI16ToF16, 0>;
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def : ReadAdvance<ReadFMovF32ToI32, 0>;
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def : ReadAdvance<ReadFMovI32ToF32, 0>;
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def : ReadAdvance<ReadFMovF64ToI64, 0>;
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def : ReadAdvance<ReadFMovI64ToF64, 0>;
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def : ReadAdvance<ReadFClass16, 0>;
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def : ReadAdvance<ReadFClass32, 0>;
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def : ReadAdvance<ReadFClass64, 0>;
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// Bitmanip
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def : ReadAdvance<ReadRotateImm, 0>;
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def : ReadAdvance<ReadRotateImm32, 0>;
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def : ReadAdvance<ReadRotateReg, 0>;
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def : ReadAdvance<ReadRotateReg32, 0>;
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def : ReadAdvance<ReadCLZ, 0>;
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def : ReadAdvance<ReadCLZ32, 0>;
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def : ReadAdvance<ReadCTZ, 0>;
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def : ReadAdvance<ReadCTZ32, 0>;
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def : ReadAdvance<ReadCPOP, 0>;
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def : ReadAdvance<ReadCPOP32, 0>;
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def : ReadAdvance<ReadORCB, 0>;
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def : ReadAdvance<ReadIMinMax, 0>;
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def : ReadAdvance<ReadREV8, 0>;
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def : ReadAdvance<ReadSHXADD, 0>;
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def : ReadAdvance<ReadSHXADD32, 0>;
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def : ReadAdvance<ReadCLMUL, 0>;
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// Single-bit instructions
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def : ReadAdvance<ReadSingleBit, 0>;
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def : ReadAdvance<ReadSingleBitImm, 0>;
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// Zfa
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def : ReadAdvance<ReadFRoundF32, 0>;
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def : ReadAdvance<ReadFRoundF64, 0>;
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def : ReadAdvance<ReadFRoundF16, 0>;
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//===----------------------------------------------------------------------===//
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// Unsupported extensions
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defm : UnsupportedSchedQ;
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defm : UnsupportedSchedV;
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defm : UnsupportedSchedZabha;
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defm : UnsupportedSchedZbkb;
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defm : UnsupportedSchedZbkx;
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defm : UnsupportedSchedZfaWithQ;
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defm : UnsupportedSchedZvk;
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defm : UnsupportedSchedSFB;
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defm : UnsupportedSchedXsf;
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}
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