This allows SDNodes to be validated against their expected type profiles and reduces the number of changes required to add a new node. There is a couple of nodes that are missing description and one node that fails validation. Part of #119709. Pull Request: https://github.com/llvm/llvm-project/pull/168120
45 lines
1.4 KiB
C++
45 lines
1.4 KiB
C++
//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "VESelectionDAGInfo.h"
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#define GET_SDNODE_DESC
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#include "VEGenSDNodeInfo.inc"
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using namespace llvm;
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VESelectionDAGInfo::VESelectionDAGInfo()
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: SelectionDAGGenTargetInfo(VEGenSDNodeInfo) {}
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VESelectionDAGInfo::~VESelectionDAGInfo() = default;
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const char *VESelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
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#define TARGET_NODE_CASE(NAME) \
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case VEISD::NAME: \
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return "VEISD::" #NAME;
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switch (static_cast<VEISD::NodeType>(Opcode)) {
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TARGET_NODE_CASE(GLOBAL_BASE_REG)
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TARGET_NODE_CASE(LEGALAVL)
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}
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#undef TARGET_NODE_CASE
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return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
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}
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void VESelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
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const SDNode *N) const {
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switch (N->getOpcode()) {
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case VEISD::GETSTACKTOP:
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// result #0 has invalid type; expected ch, got i64
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return;
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}
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SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
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}
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