llvm-project/llvm/lib/Target/VE/VESelectionDAGInfo.cpp
Sergei Barannikov 0a58e49c44
[VE] TableGen-erate SDNode descriptions (#168120)
This allows SDNodes to be validated against their expected type profiles
and reduces the number of changes required to add a new node.

There is a couple of nodes that are missing description and one node
that fails validation.

Part of #119709.

Pull Request: https://github.com/llvm/llvm-project/pull/168120
2025-11-14 22:05:57 +00:00

45 lines
1.4 KiB
C++

//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
#include "VESelectionDAGInfo.h"
#define GET_SDNODE_DESC
#include "VEGenSDNodeInfo.inc"
using namespace llvm;
VESelectionDAGInfo::VESelectionDAGInfo()
: SelectionDAGGenTargetInfo(VEGenSDNodeInfo) {}
VESelectionDAGInfo::~VESelectionDAGInfo() = default;
const char *VESelectionDAGInfo::getTargetNodeName(unsigned Opcode) const {
#define TARGET_NODE_CASE(NAME) \
case VEISD::NAME: \
return "VEISD::" #NAME;
switch (static_cast<VEISD::NodeType>(Opcode)) {
TARGET_NODE_CASE(GLOBAL_BASE_REG)
TARGET_NODE_CASE(LEGALAVL)
}
#undef TARGET_NODE_CASE
return SelectionDAGGenTargetInfo::getTargetNodeName(Opcode);
}
void VESelectionDAGInfo::verifyTargetNode(const SelectionDAG &DAG,
const SDNode *N) const {
switch (N->getOpcode()) {
case VEISD::GETSTACKTOP:
// result #0 has invalid type; expected ch, got i64
return;
}
SelectionDAGGenTargetInfo::verifyTargetNode(DAG, N);
}