4790a14199
This patch extends the X86CompressEVEX pass to recognize and compress multi-instruction masking patterns. It also adds relevant tests for the new pattern. Fixes #171746 Fixes #174871
529 lines
17 KiB
C++
529 lines
17 KiB
C++
//===- X86CompressEVEX.cpp ------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass compresses instructions from EVEX space to legacy/VEX/EVEX space
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// when possible in order to reduce code size or facilitate HW decoding.
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//
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// Possible compression:
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// a. AVX512 instruction (EVEX) -> AVX instruction (VEX)
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// b. Promoted instruction (EVEX) -> pre-promotion instruction (legacy/VEX)
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// c. NDD (EVEX) -> non-NDD (legacy)
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// d. NF_ND (EVEX) -> NF (EVEX)
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// e. NonNF (EVEX) -> NF (EVEX)
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// f. SETZUCCm (EVEX) -> SETCCm (legacy)
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// g. VPMOV*2M (EVEX) + KMOV -> VMOVMSK/VPMOVMSKB (VEX)
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//
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// Compression a, b and c can always reduce code size, with some exceptions
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// such as promoted 16-bit CRC32 which is as long as the legacy version.
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//
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// legacy:
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// crc32w %si, %eax ## encoding: [0x66,0xf2,0x0f,0x38,0xf1,0xc6]
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// promoted:
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// crc32w %si, %eax ## encoding: [0x62,0xf4,0x7d,0x08,0xf1,0xc6]
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//
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// From performance perspective, these should be same (same uops and same EXE
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// ports). From a FMV perspective, an older legacy encoding is preferred b/c it
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// can execute in more places (broader HW install base). So we will still do
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// the compression.
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//
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// Compression d can help hardware decode (HW may skip reading the NDD
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// register) although the instruction length remains unchanged.
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//
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// Compression e can help hardware skip updating EFLAGS although the instruction
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// length remains unchanged.
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/X86BaseInfo.h"
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/ADT/StringRef.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/MachinePassManager.h"
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#include "llvm/IR/Analysis.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/Pass.h"
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#include <atomic>
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#include <cassert>
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#include <cstdint>
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using namespace llvm;
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#define COMP_EVEX_DESC "Compressing EVEX instrs when possible"
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#define COMP_EVEX_NAME "x86-compress-evex"
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#define DEBUG_TYPE COMP_EVEX_NAME
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extern cl::opt<bool> X86EnableAPXForRelocation;
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namespace {
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// Including the generated EVEX compression tables.
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#define GET_X86_COMPRESS_EVEX_TABLE
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#include "X86GenInstrMapping.inc"
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class CompressEVEXLegacy : public MachineFunctionPass {
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public:
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static char ID;
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CompressEVEXLegacy() : MachineFunctionPass(ID) {}
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StringRef getPassName() const override { return COMP_EVEX_DESC; }
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bool runOnMachineFunction(MachineFunction &MF) override;
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().setNoVRegs();
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}
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};
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} // end anonymous namespace
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char CompressEVEXLegacy::ID = 0;
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static bool usesExtendedRegister(const MachineInstr &MI) {
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auto isHiRegIdx = [](MCRegister Reg) {
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// Check for XMM register with indexes between 16 - 31.
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if (Reg >= X86::XMM16 && Reg <= X86::XMM31)
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return true;
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// Check for YMM register with indexes between 16 - 31.
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if (Reg >= X86::YMM16 && Reg <= X86::YMM31)
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return true;
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// Check for GPR with indexes between 16 - 31.
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if (X86II::isApxExtendedReg(Reg))
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return true;
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return false;
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};
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// Check that operands are not ZMM regs or
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// XMM/YMM regs with hi indexes between 16 - 31.
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for (const MachineOperand &MO : MI.explicit_operands()) {
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if (!MO.isReg())
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continue;
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MCRegister Reg = MO.getReg().asMCReg();
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assert(!X86II::isZMMReg(Reg) &&
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"ZMM instructions should not be in the EVEX->VEX tables");
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if (isHiRegIdx(Reg))
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return true;
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}
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return false;
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}
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// Do any custom cleanup needed to finalize the conversion.
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static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
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(void)NewOpc;
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unsigned Opc = MI.getOpcode();
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switch (Opc) {
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case X86::VALIGNDZ128rri:
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case X86::VALIGNDZ128rmi:
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case X86::VALIGNQZ128rri:
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case X86::VALIGNQZ128rmi: {
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assert((NewOpc == X86::VPALIGNRrri || NewOpc == X86::VPALIGNRrmi) &&
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"Unexpected new opcode!");
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unsigned Scale =
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(Opc == X86::VALIGNQZ128rri || Opc == X86::VALIGNQZ128rmi) ? 8 : 4;
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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Imm.setImm(Imm.getImm() * Scale);
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break;
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}
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case X86::VSHUFF32X4Z256rmi:
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case X86::VSHUFF32X4Z256rri:
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case X86::VSHUFF64X2Z256rmi:
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case X86::VSHUFF64X2Z256rri:
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case X86::VSHUFI32X4Z256rmi:
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case X86::VSHUFI32X4Z256rri:
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case X86::VSHUFI64X2Z256rmi:
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case X86::VSHUFI64X2Z256rri: {
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assert((NewOpc == X86::VPERM2F128rri || NewOpc == X86::VPERM2I128rri ||
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NewOpc == X86::VPERM2F128rmi || NewOpc == X86::VPERM2I128rmi) &&
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"Unexpected new opcode!");
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MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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int64_t ImmVal = Imm.getImm();
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// Set bit 5, move bit 1 to bit 4, copy bit 0.
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Imm.setImm(0x20 | ((ImmVal & 2) << 3) | (ImmVal & 1));
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break;
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}
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case X86::VRNDSCALEPDZ128rri:
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case X86::VRNDSCALEPDZ128rmi:
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case X86::VRNDSCALEPSZ128rri:
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case X86::VRNDSCALEPSZ128rmi:
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case X86::VRNDSCALEPDZ256rri:
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case X86::VRNDSCALEPDZ256rmi:
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case X86::VRNDSCALEPSZ256rri:
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case X86::VRNDSCALEPSZ256rmi:
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case X86::VRNDSCALESDZrri:
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case X86::VRNDSCALESDZrmi:
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case X86::VRNDSCALESSZrri:
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case X86::VRNDSCALESSZrmi:
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case X86::VRNDSCALESDZrri_Int:
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case X86::VRNDSCALESDZrmi_Int:
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case X86::VRNDSCALESSZrri_Int:
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case X86::VRNDSCALESSZrmi_Int:
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const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
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int64_t ImmVal = Imm.getImm();
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// Ensure that only bits 3:0 of the immediate are used.
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if ((ImmVal & 0xf) != ImmVal)
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return false;
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break;
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}
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return true;
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}
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static bool isKMovNarrowing(unsigned VPMOVOpc, unsigned KMOVOpc) {
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unsigned VPMOVBits = 0;
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switch (VPMOVOpc) {
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case X86::VPMOVQ2MZ128kr:
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VPMOVBits = 2;
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break;
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case X86::VPMOVQ2MZ256kr:
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case X86::VPMOVD2MZ128kr:
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VPMOVBits = 4;
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break;
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case X86::VPMOVD2MZ256kr:
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VPMOVBits = 8;
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break;
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case X86::VPMOVB2MZ128kr:
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VPMOVBits = 16;
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break;
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case X86::VPMOVB2MZ256kr:
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VPMOVBits = 32;
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break;
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default:
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llvm_unreachable("Unknown VPMOV opcode");
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}
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unsigned KMOVSize = 0;
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switch (KMOVOpc) {
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case X86::KMOVBrk:
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KMOVSize = 8;
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break;
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case X86::KMOVWrk:
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KMOVSize = 16;
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break;
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case X86::KMOVDrk:
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KMOVSize = 32;
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break;
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default:
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llvm_unreachable("Unknown KMOV opcode");
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}
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return KMOVSize < VPMOVBits;
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}
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// Try to compress VPMOV*2M + KMOV chain patterns:
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// vpmov*2m %xmm0, %k0 -> (erase this)
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// kmov* %k0, %eax -> vmovmskp* %xmm0, %eax
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static bool tryCompressVPMOVPattern(MachineInstr &MI, MachineBasicBlock &MBB,
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const X86Subtarget &ST,
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SmallVectorImpl<MachineInstr *> &ToErase) {
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const X86InstrInfo *TII = ST.getInstrInfo();
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const TargetRegisterInfo *TRI = ST.getRegisterInfo();
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MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
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unsigned Opc = MI.getOpcode();
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if (Opc != X86::VPMOVD2MZ128kr && Opc != X86::VPMOVD2MZ256kr &&
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Opc != X86::VPMOVQ2MZ128kr && Opc != X86::VPMOVQ2MZ256kr &&
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Opc != X86::VPMOVB2MZ128kr && Opc != X86::VPMOVB2MZ256kr)
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return false;
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Register MaskReg = MI.getOperand(0).getReg();
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Register SrcVecReg = MI.getOperand(1).getReg();
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unsigned MovMskOpc = 0;
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switch (Opc) {
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case X86::VPMOVD2MZ128kr:
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MovMskOpc = X86::VMOVMSKPSrr;
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break;
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case X86::VPMOVD2MZ256kr:
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MovMskOpc = X86::VMOVMSKPSYrr;
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break;
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case X86::VPMOVQ2MZ128kr:
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MovMskOpc = X86::VMOVMSKPDrr;
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break;
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case X86::VPMOVQ2MZ256kr:
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MovMskOpc = X86::VMOVMSKPDYrr;
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break;
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case X86::VPMOVB2MZ128kr:
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MovMskOpc = X86::VPMOVMSKBrr;
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break;
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case X86::VPMOVB2MZ256kr:
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MovMskOpc = X86::VPMOVMSKBYrr;
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break;
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default:
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llvm_unreachable("Unknown VPMOV opcode");
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}
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MachineInstr *KMovMI = nullptr;
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for (MachineInstr &CurMI : llvm::make_range(
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std::next(MachineBasicBlock::iterator(MI)), MBB.end())) {
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if (CurMI.modifiesRegister(MaskReg, TRI)) {
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if (!KMovMI)
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return false; // Mask clobbered before use
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break;
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}
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if (CurMI.readsRegister(MaskReg, TRI)) {
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if (KMovMI)
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return false; // Fail: Mask has MULTIPLE uses
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unsigned UseOpc = CurMI.getOpcode();
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bool IsKMOV = UseOpc == X86::KMOVBrk || UseOpc == X86::KMOVWrk ||
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UseOpc == X86::KMOVDrk;
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// Only allow non-narrowing KMOV uses of the mask.
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if (IsKMOV && CurMI.getOperand(1).getReg() == MaskReg &&
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!isKMovNarrowing(Opc, UseOpc)) {
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KMovMI = &CurMI;
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// continue scanning to ensure
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// there are no *other* uses of the mask later in the block.
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} else {
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return false;
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}
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}
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if (!KMovMI && CurMI.modifiesRegister(SrcVecReg, TRI)) {
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return false; // SrcVecReg modified before it could be used by MOVMSK
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}
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}
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if (!KMovMI)
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return false;
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// Check if MaskReg is used in any other basic blocks
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for (const MachineOperand &MO : MRI->use_operands(MaskReg))
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if (MO.getParent()->getParent() != &MBB)
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return false;
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// Apply the transformation
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KMovMI->setDesc(TII->get(MovMskOpc));
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KMovMI->getOperand(1).setReg(SrcVecReg);
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KMovMI->setAsmPrinterFlag(X86::AC_EVEX_2_VEX);
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ToErase.push_back(&MI);
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return true;
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}
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static bool CompressEVEXImpl(MachineInstr &MI, MachineBasicBlock &MBB,
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const X86Subtarget &ST,
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SmallVectorImpl<MachineInstr *> &ToErase) {
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uint64_t TSFlags = MI.getDesc().TSFlags;
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// Check for EVEX instructions only.
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if ((TSFlags & X86II::EncodingMask) != X86II::EVEX)
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return false;
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// Instructions with mask or 512-bit vector can't be converted to VEX.
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if (TSFlags & (X86II::EVEX_K | X86II::EVEX_L2))
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return false;
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// Specialized VPMOVD2M + KMOV -> MOVMSK fold first.
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if (tryCompressVPMOVPattern(MI, MBB, ST, ToErase))
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return true;
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auto IsRedundantNewDataDest = [&](unsigned &Opc) {
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// $rbx = ADD64rr_ND $rbx, $rax / $rbx = ADD64rr_ND $rax, $rbx
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// ->
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// $rbx = ADD64rr $rbx, $rax
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const MCInstrDesc &Desc = MI.getDesc();
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Register Reg0 = MI.getOperand(0).getReg();
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const MachineOperand &Op1 = MI.getOperand(1);
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if (!Op1.isReg() || X86::getFirstAddrOperandIdx(MI) == 1 ||
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X86::isCFCMOVCC(MI.getOpcode()))
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return false;
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Register Reg1 = Op1.getReg();
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if (Reg1 == Reg0)
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return true;
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// Op1 and Op2 may be commutable for ND instructions.
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if (!Desc.isCommutable() || Desc.getNumOperands() < 3 ||
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!MI.getOperand(2).isReg() || MI.getOperand(2).getReg() != Reg0)
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return false;
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// Opcode may change after commute, e.g. SHRD -> SHLD
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ST.getInstrInfo()->commuteInstruction(MI, false, 1, 2);
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Opc = MI.getOpcode();
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return true;
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};
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// EVEX_B has several meanings.
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// AVX512:
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// register form: rounding control or SAE
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// memory form: broadcast
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//
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// APX:
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// MAP4: NDD, ZU
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//
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// For AVX512 cases, EVEX prefix is needed in order to carry this information
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// thus preventing the transformation to VEX encoding.
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bool IsND = X86II::hasNewDataDest(TSFlags);
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unsigned Opc = MI.getOpcode();
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bool IsSetZUCCm = Opc == X86::SETZUCCm;
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if (TSFlags & X86II::EVEX_B && !IsND && !IsSetZUCCm)
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return false;
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// MOVBE*rr is special because it has semantic of NDD but not set EVEX_B.
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bool IsNDLike = IsND || Opc == X86::MOVBE32rr || Opc == X86::MOVBE64rr;
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bool IsRedundantNDD = IsNDLike ? IsRedundantNewDataDest(Opc) : false;
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auto GetCompressedOpc = [&](unsigned Opc) -> unsigned {
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ArrayRef<X86TableEntry> Table = ArrayRef(X86CompressEVEXTable);
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const auto I = llvm::lower_bound(Table, Opc);
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if (I == Table.end() || I->OldOpc != Opc)
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return 0;
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if (usesExtendedRegister(MI) || !checkPredicate(I->NewOpc, &ST) ||
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!performCustomAdjustments(MI, I->NewOpc))
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return 0;
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return I->NewOpc;
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};
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Register Dst = MI.getOperand(0).getReg();
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if (IsRedundantNDD) {
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// Redundant NDD ops cannot be safely compressed if either:
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// - the legacy op would introduce a partial write that BreakFalseDeps
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// identified as a potential stall, or
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// - the op is writing to a subregister of a live register, i.e. the
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// full (zeroed) result is used.
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// Both cases are indicated by an implicit def of the superregister.
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if (Dst &&
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(X86::GR16RegClass.contains(Dst) || X86::GR8RegClass.contains(Dst))) {
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Register Super = getX86SubSuperRegister(Dst, 64);
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if (MI.definesRegister(Super, /*TRI=*/nullptr))
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IsRedundantNDD = false;
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}
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// ADDrm/mr instructions with NDD + relocation had been transformed to the
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// instructions without NDD in X86SuppressAPXForRelocation pass. That is to
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// keep backward compatibility with linkers without APX support.
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if (!X86EnableAPXForRelocation)
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assert(!isAddMemInstrWithRelocation(MI) &&
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"Unexpected NDD instruction with relocation!");
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} else if (Opc == X86::ADD32ri_ND || Opc == X86::ADD64ri32_ND ||
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Opc == X86::ADD32rr_ND || Opc == X86::ADD64rr_ND) {
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// Non-redundant NDD ADD can be compressed to LEA when:
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// - No EGPR register used and
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// - EFLAGS is dead.
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if (!usesExtendedRegister(MI) &&
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MI.registerDefIsDead(X86::EFLAGS, /*TRI=*/nullptr)) {
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Register Src1 = MI.getOperand(1).getReg();
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const MachineOperand &Src2 = MI.getOperand(2);
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bool Is32BitReg = Opc == X86::ADD32ri_ND || Opc == X86::ADD32rr_ND;
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const MCInstrDesc &NewDesc =
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ST.getInstrInfo()->get(Is32BitReg ? X86::LEA64_32r : X86::LEA64r);
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if (Is32BitReg)
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Src1 = getX86SubSuperRegister(Src1, 64);
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MachineInstrBuilder MIB = BuildMI(MBB, MI, MI.getDebugLoc(), NewDesc, Dst)
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.addReg(Src1)
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.addImm(1);
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if (Opc == X86::ADD32ri_ND || Opc == X86::ADD64ri32_ND)
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MIB.addReg(0).add(Src2);
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else if (Is32BitReg)
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MIB.addReg(getX86SubSuperRegister(Src2.getReg(), 64)).addImm(0);
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else
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MIB.add(Src2).addImm(0);
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MIB.addReg(0);
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MI.removeFromParent();
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return true;
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}
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}
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// NonNF -> NF only if it's not a compressible NDD instruction and eflags is
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// dead.
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unsigned NewOpc = IsRedundantNDD
|
|
? X86::getNonNDVariant(Opc)
|
|
: ((IsNDLike && ST.hasNF() &&
|
|
MI.registerDefIsDead(X86::EFLAGS, /*TRI=*/nullptr))
|
|
? X86::getNFVariant(Opc)
|
|
: GetCompressedOpc(Opc));
|
|
|
|
if (!NewOpc)
|
|
return false;
|
|
|
|
const MCInstrDesc &NewDesc = ST.getInstrInfo()->get(NewOpc);
|
|
MI.setDesc(NewDesc);
|
|
unsigned AsmComment;
|
|
switch (NewDesc.TSFlags & X86II::EncodingMask) {
|
|
case X86II::LEGACY:
|
|
AsmComment = X86::AC_EVEX_2_LEGACY;
|
|
break;
|
|
case X86II::VEX:
|
|
AsmComment = X86::AC_EVEX_2_VEX;
|
|
break;
|
|
case X86II::EVEX:
|
|
AsmComment = X86::AC_EVEX_2_EVEX;
|
|
assert(IsND && (NewDesc.TSFlags & X86II::EVEX_NF) &&
|
|
"Unknown EVEX2EVEX compression");
|
|
break;
|
|
default:
|
|
llvm_unreachable("Unknown EVEX compression");
|
|
}
|
|
MI.setAsmPrinterFlag(AsmComment);
|
|
if (IsRedundantNDD)
|
|
MI.tieOperands(0, 1);
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool runOnMF(MachineFunction &MF) {
|
|
LLVM_DEBUG(dbgs() << "Start X86CompressEVEXPass\n";);
|
|
#ifndef NDEBUG
|
|
// Make sure the tables are sorted.
|
|
static std::atomic<bool> TableChecked(false);
|
|
if (!TableChecked.load(std::memory_order_relaxed)) {
|
|
assert(llvm::is_sorted(X86CompressEVEXTable) &&
|
|
"X86CompressEVEXTable is not sorted!");
|
|
TableChecked.store(true, std::memory_order_relaxed);
|
|
}
|
|
#endif
|
|
const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
|
|
if (!ST.hasAVX512() && !ST.hasEGPR() && !ST.hasNDD() && !ST.hasZU())
|
|
return false;
|
|
|
|
bool Changed = false;
|
|
|
|
for (MachineBasicBlock &MBB : MF) {
|
|
SmallVector<MachineInstr *, 4> ToErase;
|
|
|
|
for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) {
|
|
Changed |= CompressEVEXImpl(MI, MBB, ST, ToErase);
|
|
}
|
|
|
|
for (MachineInstr *MI : ToErase) {
|
|
MI->eraseFromParent();
|
|
}
|
|
}
|
|
LLVM_DEBUG(dbgs() << "End X86CompressEVEXPass\n";);
|
|
return Changed;
|
|
}
|
|
|
|
INITIALIZE_PASS(CompressEVEXLegacy, COMP_EVEX_NAME, COMP_EVEX_DESC, false,
|
|
false)
|
|
|
|
FunctionPass *llvm::createX86CompressEVEXLegacyPass() {
|
|
return new CompressEVEXLegacy();
|
|
}
|
|
|
|
bool CompressEVEXLegacy::runOnMachineFunction(MachineFunction &MF) {
|
|
return runOnMF(MF);
|
|
}
|
|
|
|
PreservedAnalyses
|
|
X86CompressEVEXPass::run(MachineFunction &MF,
|
|
MachineFunctionAnalysisManager &MFAM) {
|
|
bool Changed = runOnMF(MF);
|
|
if (!Changed)
|
|
return PreservedAnalyses::all();
|
|
PreservedAnalyses PA = getMachineFunctionPassPreservedAnalyses();
|
|
PA.preserveSet<CFGAnalyses>();
|
|
return PA;
|
|
}
|