191af6c254
The llvm.cond.loop intrinsic is semantically equivalent to a conditional branch conditioned on ``pred`` to a basic block consisting only of an unconditional branch to itself. Unlike such a branch, it is guaranteed to use specific instructions. This allows an interrupt handler or other introspection mechanism to straightforwardly detect whether the program is currently spinning in the infinite loop and possibly terminate the program if so. The intent is that this intrinsic may be used as a more efficient alternative to a conditional branch to a call to ``llvm.trap`` in circumstances where the loop detection is guaranteed to be present. This construct has been experimentally determined to be executed more efficiently (when the branch is not taken) than a conditional branch to a trap instruction on AMD and older Intel microarchitectures, and is also more code size efficient by avoiding the need to emit a trap instruction and possibly a long branch instruction. On i386 and x86_64, the infinite loop is guaranteed to consist of a short conditional branch instruction that branches to itself. Specifically, the first byte of the instruction will be between 0x70 and 0x7F, and the second byte will be 0xFE. Part of this RFC: https://discourse.llvm.org/t/rfc-optimizing-conditional-traps/89456 Reviewers: arsenm, RKSimon, fmayer, vitalybuka Pull Request: https://github.com/llvm/llvm-project/pull/177686
459 lines
21 KiB
TableGen
459 lines
21 KiB
TableGen
//===-- X86InstrControl.td - Control Flow Instructions -----*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the X86 jump, return, call, and related instructions.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Control Flow Instructions.
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//
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// Return instructions.
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//
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// The X86retglue return instructions are variadic because we may add ST0 and
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// ST1 arguments when returning values on the x87 stack.
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let isTerminator = 1, isReturn = 1, isBarrier = 1,
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hasCtrlDep = 1, FPForm = SpecialFP, SchedRW = [WriteJumpLd] in {
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def RET32 : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{l}", []>, OpSize32, Requires<[Not64BitMode]>;
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def RET64 : I <0xC3, RawFrm, (outs), (ins variable_ops),
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"ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
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def RET16 : I <0xC3, RawFrm, (outs), (ins),
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"ret{w}", []>, OpSize16;
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def RETI32 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{l}\t$amt", []>, OpSize32, Requires<[Not64BitMode]>;
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def RETI64 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
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"ret{q}\t$amt", []>, OpSize32, Requires<[In64BitMode]>;
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def RETI16 : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
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"ret{w}\t$amt", []>, OpSize16;
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def LRET32 : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{l|f}", []>, OpSize32;
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def LRET64 : RI <0xCB, RawFrm, (outs), (ins),
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"{l}ret{|f}q", []>, Requires<[In64BitMode]>;
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def LRET16 : I <0xCB, RawFrm, (outs), (ins),
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"{l}ret{w|f}", []>, OpSize16;
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def LRETI32 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{l|f}\t$amt", []>, OpSize32;
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def LRETI64 : RIi16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
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def LRETI16 : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
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"{l}ret{w|f}\t$amt", []>, OpSize16;
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// The machine return from interrupt instruction, but sometimes we need to
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// perform a post-epilogue stack adjustment. Codegen emits the pseudo form
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// which expands to include an SP adjustment if necessary.
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def IRET16 : I <0xcf, RawFrm, (outs), (ins), "iret{w}", []>,
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OpSize16;
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def IRET32 : I <0xcf, RawFrm, (outs), (ins), "iret{l|d}", []>, OpSize32;
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def IRET64 : RI <0xcf, RawFrm, (outs), (ins), "iretq", []>, Requires<[In64BitMode]>;
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let isCodeGenOnly = 1 in
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def IRET : PseudoI<(outs), (ins i32imm:$adj), [(X86iret timm:$adj)]>;
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def RET : PseudoI<(outs), (ins i32imm:$adj, variable_ops), [(X86retglue timm:$adj)]>;
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}
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// Unconditional branches.
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let isBarrier = 1, isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
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"jmp\t$dst", [(br bb:$dst)]>;
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let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
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"jmp\t$dst", []>, OpSize16;
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def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
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"jmp\t$dst", []>, OpSize32;
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}
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}
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// Conditional Branches.
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let isBranch = 1, isTerminator = 1, Uses = [EFLAGS], SchedRW = [WriteJump],
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isCodeGenOnly = 1, ForceDisassemble = 1 in {
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def JCC_1 : Ii8PCRel <0x70, AddCCFrm, (outs),
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(ins brtarget8:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[(X86brcond bb:$dst, timm:$cond, EFLAGS)]>;
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let hasSideEffects = 0 in {
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def JCC_2 : Ii16PCRel<0x80, AddCCFrm, (outs),
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(ins brtarget16:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[]>, OpSize16, TB;
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def JCC_4 : Ii32PCRel<0x80, AddCCFrm, (outs),
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(ins brtarget32:$dst, ccode:$cond),
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"j${cond}\t$dst",
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[]>, TB, OpSize32;
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}
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}
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let hasSideEffects = 1, Uses = [EFLAGS], SchedRW = [WriteJump] in
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def JCC_SELF : PseudoI<(outs), (ins ccode:$cond),
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[(X86brcond_self timm:$cond, EFLAGS)]>;
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// jcx/jecx/jrcx instructions.
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let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
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// These are the 32-bit versions of this instruction for the asmparser. In
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// 32-bit mode, the address size prefix is jcxz and the unprefixed version is
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// jecxz.
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let Uses = [CX] in
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def JCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"jcxz\t$dst", []>, AdSize16, Requires<[Not64BitMode]>;
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let Uses = [ECX] in
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def JECXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"jecxz\t$dst", []>, AdSize32;
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let Uses = [RCX] in
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def JRCXZ : Ii8PCRel<0xE3, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"jrcxz\t$dst", []>, AdSize64, Requires<[In64BitMode]>;
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}
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// Indirect branches
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let isBranch = 1, isTerminator = 1, isBarrier = 1, isIndirectBranch = 1 in {
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def JMP16r : I<0xFF, MRM4r, (outs), (ins GR16:$dst), "jmp{w}\t{*}$dst",
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[(brind GR16:$dst)]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJump]>;
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def JMP16m : I<0xFF, MRM4m, (outs), (ins i16mem:$dst), "jmp{w}\t{*}$dst",
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[(brind (loadi16 addr:$dst))]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJumpLd]>;
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def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l}\t{*}$dst",
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[(brind GR32:$dst)]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJump]>;
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def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l}\t{*}$dst",
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[(brind (loadi32 addr:$dst))]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJumpLd]>;
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def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q}\t{*}$dst",
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[(brind GR64:$dst)]>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>;
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def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q}\t{*}$dst",
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[(brind (loadi64 addr:$dst))]>, Requires<[In64BitMode]>,
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Sched<[WriteJumpLd]>;
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// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
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// These are switched from TAILJMPr/m64_REX in MCInstLower.
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let isCodeGenOnly = 1, hasREX_W = 1 in {
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def JMP64r_REX : I<0xFF, MRM4r, (outs), (ins GR64:$dst),
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"rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJump]>;
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let mayLoad = 1 in
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def JMP64m_REX : I<0xFF, MRM4m, (outs), (ins i64mem:$dst),
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"rex64 jmp{q}\t{*}$dst", []>, Sched<[WriteJumpLd]>;
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}
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// Non-tracking jumps for IBT, use with caution.
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let isCodeGenOnly = 1 in {
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def JMP16r_NT : I<0xFF, MRM4r, (outs), (ins GR16 : $dst), "jmp{w}\t{*}$dst",
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[(X86NoTrackBrind GR16 : $dst)]>, Requires<[Not64BitMode]>,
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OpSize16, Sched<[WriteJump]>, NOTRACK;
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def JMP16m_NT : I<0xFF, MRM4m, (outs), (ins i16mem : $dst), "jmp{w}\t{*}$dst",
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[(X86NoTrackBrind (loadi16 addr : $dst))]>,
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Requires<[Not64BitMode]>, OpSize16, Sched<[WriteJumpLd]>,
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NOTRACK;
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def JMP32r_NT : I<0xFF, MRM4r, (outs), (ins GR32 : $dst), "jmp{l}\t{*}$dst",
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[(X86NoTrackBrind GR32 : $dst)]>, Requires<[Not64BitMode]>,
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OpSize32, Sched<[WriteJump]>, NOTRACK;
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def JMP32m_NT : I<0xFF, MRM4m, (outs), (ins i32mem : $dst), "jmp{l}\t{*}$dst",
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[(X86NoTrackBrind (loadi32 addr : $dst))]>,
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Requires<[Not64BitMode]>, OpSize32, Sched<[WriteJumpLd]>,
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NOTRACK;
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def JMP64r_NT : I<0xFF, MRM4r, (outs), (ins GR64 : $dst), "jmp{q}\t{*}$dst",
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[(X86NoTrackBrind GR64 : $dst)]>, Requires<[In64BitMode]>,
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Sched<[WriteJump]>, NOTRACK;
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def JMP64m_NT : I<0xFF, MRM4m, (outs), (ins i64mem : $dst), "jmp{q}\t{*}$dst",
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[(X86NoTrackBrind(loadi64 addr : $dst))]>,
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Requires<[In64BitMode]>, Sched<[WriteJumpLd]>, NOTRACK;
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}
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let Predicates = [Not64BitMode], AsmVariantName = "att" in {
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def FARJMP32i : Iseg32<0xEA, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"ljmp{l}\t$seg, $off", []>,
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OpSize32, Sched<[WriteJump]>;
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def FARJMP16i : Iseg16<0xEA, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"ljmp{w}\t$seg, $off", []>,
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OpSize16, Sched<[WriteJump]>;
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}
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let mayLoad = 1 in {
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def FARJMP64m : RI<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"ljmp{q}\t{*}$dst", []>, Sched<[WriteJump]>, Requires<[In64BitMode]>;
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def FARJMP32m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"{l}jmp{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
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let AsmVariantName = "att" in
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def FARJMP16m : I<0xFF, MRM5m, (outs), (ins opaquemem:$dst),
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"ljmp{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
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}
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}
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def JMPABS64i : Ii64<0xA1, RawFrm, (outs), (ins i64imm:$dst), "jmpabs\t$dst", []>,
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ExplicitREX2Prefix, Requires<[In64BitMode]>, Sched<[WriteJumpLd]>;
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// Loop instructions
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let isBranch = 1, isTerminator = 1, SchedRW = [WriteJump] in {
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def LOOP : Ii8PCRel<0xE2, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"loop\t$dst", []>;
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def LOOPE : Ii8PCRel<0xE1, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"loope\t$dst", []>;
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def LOOPNE : Ii8PCRel<0xE0, RawFrm, (outs), (ins i8imm_brtarget:$dst),
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"loopne\t$dst", []>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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let isCall = 1 in
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// All calls clobber the non-callee saved registers. ESP is marked as
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// a use to prevent stack-pointer assignments that appear immediately
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// before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let Uses = [ESP, SSP] in {
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def CALLpcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i32imm_brtarget:$dst),
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"call{l}\t$dst", []>, OpSize32,
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Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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let hasSideEffects = 0 in
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def CALLpcrel16 : Ii16PCRel<0xE8, RawFrm,
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(outs), (ins i16imm_brtarget:$dst),
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"call{w}\t$dst", []>, OpSize16,
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Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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def CALL16r : I<0xFF, MRM2r, (outs), (ins GR16:$dst),
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"call{w}\t{*}$dst", [(X86call GR16:$dst)]>,
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OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>;
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def CALL16m : I<0xFF, MRM2m, (outs), (ins i16mem:$dst),
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"call{w}\t{*}$dst", [(X86call (loadi16 addr:$dst))]>,
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OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>;
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def CALL32r : I<0xFF, MRM2r, (outs), (ins GR32:$dst),
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"call{l}\t{*}$dst", [(X86call GR32:$dst)]>, OpSize32,
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Requires<[Not64BitMode,NotUseIndirectThunkCalls]>,
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Sched<[WriteJump]>;
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def CALL32m : I<0xFF, MRM2m, (outs), (ins i32mem:$dst),
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"call{l}\t{*}$dst", [(X86call (loadi32 addr:$dst))]>,
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OpSize32,
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Requires<[Not64BitMode,FavorMemIndirectCall,
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NotUseIndirectThunkCalls]>,
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Sched<[WriteJumpLd]>;
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// Non-tracking calls for IBT, use with caution.
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let isCodeGenOnly = 1 in {
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def CALL16r_NT : I<0xFF, MRM2r, (outs), (ins GR16 : $dst),
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"call{w}\t{*}$dst",[(X86NoTrackCall GR16 : $dst)]>,
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OpSize16, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
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def CALL16m_NT : I<0xFF, MRM2m, (outs), (ins i16mem : $dst),
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"call{w}\t{*}$dst",[(X86NoTrackCall(loadi16 addr : $dst))]>,
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OpSize16, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>, NOTRACK;
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def CALL32r_NT : I<0xFF, MRM2r, (outs), (ins GR32 : $dst),
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"call{l}\t{*}$dst",[(X86NoTrackCall GR32 : $dst)]>,
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OpSize32, Requires<[Not64BitMode]>, Sched<[WriteJump]>, NOTRACK;
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def CALL32m_NT : I<0xFF, MRM2m, (outs), (ins i32mem : $dst),
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"call{l}\t{*}$dst",[(X86NoTrackCall(loadi32 addr : $dst))]>,
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OpSize32, Requires<[Not64BitMode,FavorMemIndirectCall]>,
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Sched<[WriteJumpLd]>, NOTRACK;
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}
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let Predicates = [Not64BitMode], AsmVariantName = "att" in {
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def FARCALL32i : Iseg32<0x9A, RawFrmImm16, (outs),
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(ins i32imm:$off, i16imm:$seg),
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"lcall{l}\t$seg, $off", []>,
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OpSize32, Sched<[WriteJump]>;
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def FARCALL16i : Iseg16<0x9A, RawFrmImm16, (outs),
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(ins i16imm:$off, i16imm:$seg),
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"lcall{w}\t$seg, $off", []>,
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OpSize16, Sched<[WriteJump]>;
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}
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let mayLoad = 1 in {
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def FARCALL32m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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"{l}call{l}\t{*}$dst", []>, OpSize32, Sched<[WriteJumpLd]>;
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def FARCALL16m : I<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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"lcall{w}\t{*}$dst", []>, OpSize16, Sched<[WriteJumpLd]>;
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}
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}
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// Tail call stuff.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, Uses = [ESP, SSP] in {
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def TCRETURNdi : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$offset),
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[]>, Sched<[WriteJump]>;
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def TCRETURNri : PseudoI<(outs), (ins GR32_TC:$dst, i32imm:$offset),
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[]>, Sched<[WriteJump]>;
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def TCRETURN_HIPE32ri : PseudoI<(outs), (ins GR32:$dst, i32imm:$offset),
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[]>, Sched<[WriteJump]>;
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let mayLoad = 1 in
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def TCRETURNmi : PseudoI<(outs), (ins i32mem_TC:$dst, i32imm:$offset),
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[]>, Sched<[WriteJumpLd]>;
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def TAILJMPd : PseudoI<(outs), (ins i32imm_brtarget:$dst),
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[]>, Sched<[WriteJump]>;
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def TAILJMPr : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
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[]>, Sched<[WriteJump]>;
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let mayLoad = 1 in
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def TAILJMPm : PseudoI<(outs), (ins i32mem_TC:$dst),
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[]>, Sched<[WriteJumpLd]>;
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}
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// Conditional tail calls are similar to the above, but they are branches
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// rather than barriers, and they use EFLAGS.
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let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
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isCodeGenOnly = 1, SchedRW = [WriteJump] in
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let Uses = [ESP, EFLAGS, SSP] in {
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def TCRETURNdicc : PseudoI<(outs),
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(ins i32imm_brtarget:$dst, i32imm:$offset, i32imm:$cond),
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[]>;
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// This gets substituted to a conditional jump instruction in MC lowering.
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def TAILJMPd_CC : PseudoI<(outs), (ins i32imm_brtarget:$dst, i32imm:$cond), []>;
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}
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//===----------------------------------------------------------------------===//
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// Call Instructions...
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//
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// RSP is marked as a use to prevent stack-pointer assignments that appear
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// immediately before calls from potentially appearing dead. Uses for argument
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// registers are added manually.
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let isCall = 1, Uses = [RSP, SSP], SchedRW = [WriteJump] in {
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// NOTE: this pattern doesn't match "X86call imm", because we do not know
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// that the offset between an arbitrary immediate and the call will fit in
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// the 32-bit pcrel field that we have.
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def CALL64pcrel32 : Ii32PCRel<0xE8, RawFrm,
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(outs), (ins i64i32imm_brtarget:$dst),
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"call{q}\t$dst", []>, OpSize32,
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Requires<[In64BitMode]>;
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def CALL64r : I<0xFF, MRM2r, (outs), (ins GR64:$dst),
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"call{q}\t{*}$dst", [(X86call GR64:$dst)]>,
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Requires<[In64BitMode,NotUseIndirectThunkCalls,ImportCallOptimizationDisabled]>;
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def CALL64m : I<0xFF, MRM2m, (outs), (ins i64mem:$dst),
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"call{q}\t{*}$dst", [(X86call (loadi64 addr:$dst))]>,
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Requires<[In64BitMode,FavorMemIndirectCall,
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|
NotUseIndirectThunkCalls]>;
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|
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// Non-tracking calls for IBT, use with caution.
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let isCodeGenOnly = 1 in {
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def CALL64r_NT : I<0xFF, MRM2r, (outs), (ins GR64 : $dst),
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"call{q}\t{*}$dst",[(X86NoTrackCall GR64 : $dst)]>,
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Requires<[In64BitMode]>, NOTRACK;
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|
def CALL64m_NT : I<0xFF, MRM2m, (outs), (ins i64mem : $dst),
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"call{q}\t{*}$dst",
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[(X86NoTrackCall(loadi64 addr : $dst))]>,
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|
Requires<[In64BitMode,FavorMemIndirectCall]>, NOTRACK;
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|
}
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|
|
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let mayLoad = 1 in
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|
def FARCALL64m : RI<0xFF, MRM3m, (outs), (ins opaquemem:$dst),
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|
"lcall{q}\t{*}$dst", []>;
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|
}
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|
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let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
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isCodeGenOnly = 1, Uses = [RSP, SSP] in {
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|
def TCRETURNdi64 : PseudoI<(outs),
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|
(ins i64i32imm_brtarget:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJump]>;
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|
def TCRETURNri64 : PseudoI<(outs),
|
|
(ins GR64_TC:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJump]>;
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|
def TCRETURN_WIN64ri : PseudoI<(outs), (ins GR64_TCW64:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJump]>;
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|
|
|
def TCRETURNri64_ImpCall : PseudoI<(outs),
|
|
(ins GR64_A:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJump]>;
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|
|
|
let mayLoad = 1 in
|
|
def TCRETURNmi64 : PseudoI<(outs),
|
|
(ins i64mem_TC:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJumpLd]>;
|
|
let mayLoad = 1 in
|
|
def TCRETURN_WINmi64 : PseudoI<(outs),
|
|
(ins i64mem_w64TC:$dst, i32imm:$offset),
|
|
[]>, Sched<[WriteJumpLd]>;
|
|
|
|
def TAILJMPd64 : PseudoI<(outs), (ins i64i32imm_brtarget:$dst),
|
|
[]>, Sched<[WriteJump]>;
|
|
|
|
def TAILJMPr64 : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
|
|
[]>, Sched<[WriteJump]>;
|
|
|
|
let mayLoad = 1 in
|
|
def TAILJMPm64 : PseudoI<(outs), (ins i64mem_TC:$dst),
|
|
[]>, Sched<[WriteJumpLd]>;
|
|
|
|
// Win64 wants indirect jumps leaving the function to have a REX_W prefix.
|
|
let hasREX_W = 1 in {
|
|
def TAILJMPr64_REX : PseudoI<(outs), (ins ptr_rc_tailcall:$dst),
|
|
[]>, Sched<[WriteJump]>;
|
|
|
|
let mayLoad = 1 in
|
|
def TAILJMPm64_REX : PseudoI<(outs), (ins i64mem_TC:$dst),
|
|
[]>, Sched<[WriteJumpLd]>;
|
|
}
|
|
}
|
|
|
|
let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
|
|
Uses = [RSP, SSP],
|
|
usesCustomInserter = 1,
|
|
SchedRW = [WriteJump] in {
|
|
def INDIRECT_THUNK_CALL32 :
|
|
PseudoI<(outs), (ins GR32:$dst), [(X86call GR32:$dst)]>,
|
|
Requires<[Not64BitMode,UseIndirectThunkCalls]>;
|
|
|
|
def INDIRECT_THUNK_CALL64 :
|
|
PseudoI<(outs), (ins GR64:$dst), [(X86call GR64:$dst)]>,
|
|
Requires<[In64BitMode,UseIndirectThunkCalls]>;
|
|
|
|
// Indirect thunk variant of indirect tail calls.
|
|
let isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
|
def INDIRECT_THUNK_TCRETURN64 :
|
|
PseudoI<(outs), (ins GR64:$dst, i32imm:$offset), []>;
|
|
def INDIRECT_THUNK_TCRETURN32 :
|
|
PseudoI<(outs), (ins GR32:$dst, i32imm:$offset), []>;
|
|
}
|
|
}
|
|
|
|
let isPseudo = 1, isCall = 1, isCodeGenOnly = 1,
|
|
Uses = [RSP, SSP],
|
|
SchedRW = [WriteJump] in {
|
|
def CALL64m_RVMARKER :
|
|
PseudoI<(outs), (ins i64imm:$rvfunc, i64mem:$dst), [(X86call_rvmarker tglobaladdr:$rvfunc, (loadi64 addr:$dst))]>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
def CALL64r_RVMARKER :
|
|
PseudoI<(outs), (ins i64imm:$rvfunc, GR64:$dst), [(X86call_rvmarker tglobaladdr:$rvfunc, GR64:$dst)]>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
def CALL64pcrel32_RVMARKER :
|
|
PseudoI<(outs), (ins i64imm:$rvfunc, i64i32imm_brtarget:$dst), []>,
|
|
Requires<[In64BitMode]>;
|
|
|
|
def CALL64r_ImpCall :
|
|
PseudoI<(outs), (ins GR64_A:$dst), [(X86call GR64_A:$dst)]>,
|
|
Requires<[In64BitMode,NotUseIndirectThunkCalls,ImportCallOptimizationEnabled]>;
|
|
}
|
|
|
|
// Conditional tail calls are similar to the above, but they are branches
|
|
// rather than barriers, and they use EFLAGS.
|
|
let isCall = 1, isTerminator = 1, isReturn = 1, isBranch = 1,
|
|
isCodeGenOnly = 1, SchedRW = [WriteJump] in
|
|
let Uses = [RSP, EFLAGS, SSP] in {
|
|
def TCRETURNdi64cc : PseudoI<(outs),
|
|
(ins i64i32imm_brtarget:$dst, i32imm:$offset,
|
|
i32imm:$cond), []>;
|
|
|
|
// This gets substituted to a conditional jump instruction in MC lowering.
|
|
def TAILJMPd64_CC : PseudoI<(outs),
|
|
(ins i64i32imm_brtarget:$dst, i32imm:$cond), []>;
|
|
}
|